Sep 22, 2009 #1 B billylee Junior Member level 1 Joined Sep 10, 2009 Messages 16 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Korea Activity points 1,390 Hi everyone I need your help I have some problem verdi compiling with mixed vlog & vhdl source my file list top.v sub0.v sub1.v sub2.v sub3.v sub4.vhd sub4_0.vhd sub4_1.vhd so I make flist like this top.v sub0.v sub1.v sub2.v sub3.v sub4.vhd -vhdl sub4_0.vhd -vhdl sub4_1.vhd & verdi -sv -f flist but this is not work what can I try next step? have a goodday!
Hi everyone I need your help I have some problem verdi compiling with mixed vlog & vhdl source my file list top.v sub0.v sub1.v sub2.v sub3.v sub4.vhd sub4_0.vhd sub4_1.vhd so I make flist like this top.v sub0.v sub1.v sub2.v sub3.v sub4.vhd -vhdl sub4_0.vhd -vhdl sub4_1.vhd & verdi -sv -f flist but this is not work what can I try next step? have a goodday!
Sep 23, 2009 #2 L ljxpjpjljx Advanced Member level 3 Joined May 5, 2008 Messages 968 Helped 81 Reputation 164 Reaction score 57 Trophy points 1,308 Location Shang Hai Activity points 4,679 -sv option is the "system verilog" compile option! vericom is the compiler for the verilog code and vhdlcom is the compiler for the vhdl code!
-sv option is the "system verilog" compile option! vericom is the compiler for the verilog code and vhdlcom is the compiler for the vhdl code!
Sep 23, 2009 #3 B billylee Junior Member level 1 Joined Sep 10, 2009 Messages 16 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location Korea Activity points 1,390 hello ljxpjpjljx thanks to your reply but I'm wondering about linking skill for mixed structure not -sv option, -sv option is needless at this source code, sorry for your confusing but thanx a lot
hello ljxpjpjljx thanks to your reply but I'm wondering about linking skill for mixed structure not -sv option, -sv option is needless at this source code, sorry for your confusing but thanx a lot