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I think it is still worthy learning Vera (or specman) because these two
languages are widely used in the industry.
Even assuming that SystemVerilog is accepted by the industry as a "de fato" standard for verification, Vera and specman (because of legacy reasons since there are millions of line of code written in these two languages) will still be around for a while.
IEEE forum attendees support SystemVerilog
By Richard Goering, EE Times
Jun 3, 2003 (6:49 PM)
URL: h**p://www.eedesign.com/story/OEG20030603S0048
ANAHEIM, Calif. — Attendees at an IEEE 1364 working group forum at the Design Automation Conference here Tuesday (June 3) asked for SystemVerilog 3.1 to be part of the emerging IEEE 1364-2005 Verilog standard — along with a host of other enhancements. The meeting marked the IEEE's first attempt to gather user input as it begins to assemble the next generation of Verilog.
The IEEE 1364 called its user forum independently from the Accellera standards organization, and solicited input from many sources, with a deadline of August 2003. That caused some political infighting between Accellera and the IEEE, raising questions about whether the standard eventually approved by the IEEE will be fully compatible with SystemVerilog 3.1.
If sentiment at the DAC user forum is any indication, 1364-2005 Verilog will include SystemVerilog 3.1. But the sparsely-attended forum didn't have enough users to reach any firm conclusions, noted moderator Kurt Baty, computer architect at WSFDB Consulting. "We've got to get a room with a bunch of users in it," he said.
Still to be determined is whether Accellera will be able to meet the IEEE's August 2003 deadline for technology donations. "The ball is in Accellera's court to donate SystemVerilog," said consultant Stu Sutherland, who serves on both the Accellera SystemVerilog and IEEE 1364 committees. "If Accellera doesn't do it, we run the risk of the IEEE duplicating a lot of effort."
Baty asked forum participants to make suggestions for a "top five" wish list for IEEE 1364-2005. One suggestion was, quite simply, SystemVerilog 3.1. When Baty asked, "is there anyone here who does not want SystemVerilog in total to be part of this standard?" only one of the 20-odd participants raised his hand.
The lone dissenter was Jay Lawrence, senior architect for functional verification at Cadence Design Systems, which has been the most skeptical EDA vendor with respect to SystemVerilog. Cadence announced Monday that it is donating technology to IEEE 1364, some of which, in the testbench generation area, overlaps with SystemVerilog 3.1.
"I like all of these things [in SystemVerilog 3.1] but not equally," said Lawrence, who argued for more user feedback on some portions of the newly-approved Accellera standard.
Others started to question whether all of SystemVerilog 3.1 will sail through the IEEE. "Just because we're bringing in SystemVerilog doesn't mean we're rubber-stamping it," said consultant Cliff Cummings. "I can't imagine the Vera stuff will go into the IEEE standard," said Baty. The Synopsys Vera language is the basis of some testbench constructs in SystemVerilog 3.1.
Forum participants liked many other suggestions for 1364-2005 that go well beyond SystemVerilog 3.1. For example, IP encryption — a technology donated by Cadence that is not found in SystemVerilog 3.1 — was a popular choice. So was the idea of separately compiled modules, a technology that Fintronic USA has promised to donate.
Some other popular suggestions included a functional coverage capture mechanism, a standard pragma capability, value charge dump (VCD) file enhancements, company-scoped attributes, resolving "disable" statement ambiguity, and removing the ACC access library of the Programming Language Interface (PLI). Forum participants also strongly supported completing unfinished features in the 1364-2001 standard.
Suggestions that didn't get as much support included global wire types, configuration views, interoperability with other design languages, a "Verilog lite" sub-standard, and Baty's own suggestion for variable-width floating point variables.
Noting that Verilog 2001 is still not complete, Baty challenged the notion that Verilog 2005 will make its stated schedule. "Do you think this will actually get done in 2005? You haven't designed any ASICs, have you? It's probably closer to 2007," he said.
Baty asked for a vote on when people thought the standard would actually be complete, and responses ranged from 2005 to 2008. "Let's stick with 2005 but open and start a PAR [project authorization request] for 2008," Sutherland suggested.
I would say within 2 years SystemVerilog
will be supported. In any case, specman,
vera and systemverilog are all so easy
to learn (once you know verilog or
vhdl), that there is no reason to
concerne oneself with learning them
until you need them.
Besides, SystemVerilog is supposed to be very similar to Verilog with a bunck of new statements added for verification.
But I heard that some companies don't want it to be adopted as a standard because Synopsys didn't donate the whole language. It seems it kept part of the language as proprietary. Maybe someone can confirm this.
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