[SOLVED] Vector translation

[jishnuv33]

I'm working with some ATE tests .I need to convert the simulation VCD to STIL or SVF format .Anyone have any idea regarding the conversion.Or anyone used Synopsys VTRAN tool.
Please reply.

 

[dpaul]

If a tool is not out there, the ASIC test guy normally use scripts for such translation. Use Bash, Pearl, Python....
This might help...

VCD to ATE vector conversion

I need to write a script to convert VCD/EVCD/LSI files to ATE format(Teradyne/Verigy) - Can anyone help me to get started with this? How do I go about starting this task? I do not and will not have access to ANY commercial softwares. I will have to write is all my self. Thank you very much.

www.edaboard.com

 

[aliarifat794]

To convert a Value Change Dump (VCD) file to STIL (Standard Test Interface Language) or SVF (Serial Vector Format), you can use tools like Synopsys VTRAN.

 

[jishnuv33]

To convert a Value Change Dump (VCD) file to STIL (Standard Test Interface Language) or SVF (Serial Vector Format), you can use tools like Synopsys VTRAN.

how to write command file for the VTRAN tool to understand the tool that event is being converted to cycles.Whether will get any example command file for that.I'm very new to this conversion.

 

[jishnuv33]

With VTRAN tool I'm able to convert the value change dump (VCD) to STIL.Thanks for help.

{ ORIGINAL VECTOR FILE-BLOCK }
ovf_block
   begin
      ORIG_FILE = "ate.vcd";
      SCRIPT_FORMAT VERILOG_VCD;
      INPUTS jtag_tms,jtag_tdi;
      OUTPUTS jtag_tdo;
   end;
{ PROCESSING-BLOCK }
proc_block
   begin
      DONT_CARE = "X";
      DISABLE_VECTOR_FILTER;
      STATE_TRANS pure_inputs 'X'->'N', 'x'->'N', 'z'->'Z';
      STATE_TRANS bidir_inputs 'X'->'N', 'x'->'N', 'z'->'Z';
      STATE_TRANS pure_outputs '1'->'H', '0'->'L', 'x'->'X', 'Z'->'T', 'z'->'T';
      STATE_TRANS bidir_outputs '1'->'H', '0'->'L', 'x'->'X', 'Z'->'T', 'z'->'T';
      CYCLE = 10;
      PINTYPE STB
          jtag_tdo
        @ 10 ;
      PINTYPE NRZ
          jtag_tms
          jtag_tdi
        @ 10 ;
   end;
{ TARGET VECTOR FILE-BLOCK }
tvf_block
   begin
      TARGET_FILE = "test.stil";
      TESTER_FORMAT STIL;
   end;
end