Vdd/Vcc noise, slow rise time CMOS input impact

One can also see the open loop voltage gain from the above noise sensitivity test.


We often take for granted that computers with billions of logic transitions per second never have logic errors ( that we know of). This can be predicted by using the clipped waveforms of logic with a known relationship SNR vs BER log curve. If a 40 dB SNR translates into a bit error rate (BER) of 10e-12, that is not good enough for computer logic at Tera-flop speeds. It might improve an order of magnitude per 1dB in SNR. However non-linear noise often becomes more significant than Gaussian Noise.

As Dana has well-demonstrated here is that 5V/100mV rms or 50:1 or 34 dB is a certainly problem. Sometimes SNR is expressed as p-p jitter and there are conversion factors for rms to p-p random and non-random noise.


PSU filtering IC decoupling must never be taken for granted as the rejection ratio of supply noise must be fully understood in SNR terms and how this translates into future errors. Each Gate has a crossover change in shootthru current Ron*Coss that draws current from both Vdd &Vss using the bypass cap ESR*C to attenuate the injected noise. a 0.1 uF cap might have an ESR of 5 Ohms or 0.5 Ohms, which values you choose for C and ESR depends on the size of the IC to improve the otherwise injected low SNR onto the supply. It can be modeled as an RC to RC attenuator with Vdd pp noise with spectral risetimes to determine the BW=0.35/Tr.

For measuring PSU noise on logic, as a former Test Engineer, I would prefer to use a cap on board from Vdd to a 50 Ohm coax to a spectrum analyzer or DSO terminated with 50 Ohms.

Is 50 dB SNR good enough or 60 dB? or ?? on Logic supply and ground noise? I'll let you think about rise times and supply noise sensitivity.