DoctorX
Member level 4
I use Cadence IC5.0 and NCSU CDK 1.2. To expose the problem:
1. Design a CMOS inverter cell in any technology (such as TSMC0.18um, HP14tB), do its layout, do extraction.
2. Construct a top-level circuit (test bench) that simulates the inv cell using a vdc power supply and a source.
3. Use Analog Environment, do show/create final netlist, you will find that the vdd! and gnd! are (wrongly) shown as something else, such as 2 and 5, in the inv subcircuit.
Observations:
1. This only happens with Cadence IC5.0. It does not happen with IC4.46, even the NCSU CDK is unchanged.
2. This happens for all simulators, Spectre, SpectreS, cdsSpice, etc.
3. This happens anytime you have the same name (such as peach!) in the top level schematic view and a lower level extracted view. It must be with the bang (!) to make it happen. Regular pins, such as peach, work ok.
4. If you have vdd! pins in layout, but you do NOT have vdd! in the top-level test bench circuit (say use vcc! instead), then the vdd! in subckt is netlisted correctly.
5. The LVS netlists works correctly. It is only the netlister for simulation.
6. This happens for most technologies (I have not tried all, but most).
7. If the top-level and lower-level views are both schematic, it works fine. It only happens when the lower-level is extracted view.
It has bothered me for almost a year. Anybody got an interest please see my attached sample library to expose the problem.
1. Design a CMOS inverter cell in any technology (such as TSMC0.18um, HP14tB), do its layout, do extraction.
2. Construct a top-level circuit (test bench) that simulates the inv cell using a vdc power supply and a source.
3. Use Analog Environment, do show/create final netlist, you will find that the vdd! and gnd! are (wrongly) shown as something else, such as 2 and 5, in the inv subcircuit.
Observations:
1. This only happens with Cadence IC5.0. It does not happen with IC4.46, even the NCSU CDK is unchanged.
2. This happens for all simulators, Spectre, SpectreS, cdsSpice, etc.
3. This happens anytime you have the same name (such as peach!) in the top level schematic view and a lower level extracted view. It must be with the bang (!) to make it happen. Regular pins, such as peach, work ok.
4. If you have vdd! pins in layout, but you do NOT have vdd! in the top-level test bench circuit (say use vcc! instead), then the vdd! in subckt is netlisted correctly.
5. The LVS netlists works correctly. It is only the netlister for simulation.
6. This happens for most technologies (I have not tried all, but most).
7. If the top-level and lower-level views are both schematic, it works fine. It only happens when the lower-level is extracted view.
It has bothered me for almost a year. Anybody got an interest please see my attached sample library to expose the problem.