vdd! and gnd! lost in netlisting extracted view

[DoctorX]

I use Cadence IC5.0 and NCSU CDK 1.2. To expose the problem:

1. Design a CMOS inverter cell in any technology (such as TSMC0.18um, HP14tB), do its layout, do extraction.
2. Construct a top-level circuit (test bench) that simulates the inv cell using a vdc power supply and a source.
3. Use Analog Environment, do show/create final netlist, you will find that the vdd! and gnd! are (wrongly) shown as something else, such as 2 and 5, in the inv subcircuit.

Observations:
1. This only happens with Cadence IC5.0. It does not happen with IC4.46, even the NCSU CDK is unchanged.
2. This happens for all simulators, Spectre, SpectreS, cdsSpice, etc.
3. This happens anytime you have the same name (such as peach!) in the top level schematic view and a lower level extracted view. It must be with the bang (!) to make it happen. Regular pins, such as peach, work ok.
4. If you have vdd! pins in layout, but you do NOT have vdd! in the top-level test bench circuit (say use vcc! instead), then the vdd! in subckt is netlisted correctly.
5. The LVS netlists works correctly. It is only the netlister for simulation.
6. This happens for most technologies (I have not tried all, but most).
7. If the top-level and lower-level views are both schematic, it works fine. It only happens when the lower-level is extracted view.

It has bothered me for almost a year. Anybody got an interest please see my attached sample library to expose the problem.

 

[sunking]

They act as gloabl env.
Search the netlist, you will find *.gloabl

 

[DoctorX]

They act as gloabl env.
Search the netlist, you will find *.gloabl

Yes, this is quite true. However, it is not the error. Please see netlist below. I have replaced: vdd! by peach!, gnd! by peachgnd!, just to show that any time you have the same global/hidden pin in

Top level: schematic
Lower level: extracted

you lose the lower level global pins. The extracted view is extracted by NCSU CDK 1.3. It works under IC4.46 but not IC5.0. Maybe the netlister has been changed?

* schematic/netlist/InvPeachBang_test.C.raw
* Netlist output for spectreS.
* Generated on Sep 3 15:44:19 2004

* global net definitions
.GLOBAL peachgnd\! peach\!

simulator lang= spectre
* File name: GlobalTest_InvPeachBang_test_schematic.S.
* Subcircuit for cell: InvPeachBang_test.
* Generated for: spectreS.
* Generated on Sep 3 15:44:20 2004.

xi2 (net3 net2) InvPeachBang_g1
c0 (net2 peachgnd\!) capacitor c=1e-12
v1 (net3 peachgnd\!) vsource type= dc
v0 (peach\! peachgnd\!) vsource type= dc dc=3.3
simulator lang= spice


simulator lang= spectre
simulator lang= spice

* File name: GlobalTest_InvPeachBang_extracted.S.
* Subcircuit for cell: InvPeachBang.
* Generated for: spectreS.
* Generated on Sep 3 15:44:19 2004.

simulator lang= spectre
* terminal mapping: A = a
* Y = y
subckt InvPeachBang_g1 a y
m1 (y a 2 2) *Here is the error! should be peach\! peach\!* hp14tbP region= sat w=1.2e-6 l=600e-9 as=1.80000003617564e-12
+ad=1.80000003617564e-12 ps=4.20000014855759e-6 pd=4.20000014855759e-6 m=1
m4 (y a 5 5) *Here is the error! should be peachgnd\! peachgnd\!* hp14tbN region= sat w=1.2e-6 l=600e-9 as=1.80000003617564e-12
+ad=1.80000003617564e-12 ps=4.20000014855759e-6 pd=4.20000014855759e-6 m=1
simulator lang= spice

simulator lang= spectre
* End of subcircuit definition.
ends InvPeachBang_g1

 

[Hughes]

I have ever encountered a similar problem:
Analog Artist did not treat 'vdd!' and 'gnd!' nets as global nets. It assigned hierarchy names like 'I1/vdd!' and 'I1/gnd!' to them however. This problem is not always occur. Sometimes it works properly and sometimes not. When I am suffering from this problem, I just rename the power name in the layout to 'VDD' and 'VSS', then treat them as nomal pins.

 

[DoctorX]

When I am suffering from this problem, I just rename the power name in the layout to 'VDD' and 'VSS', then treat them as nomal pins.

This is exactly what I did. However, I am still interested in shooting out the real problem. Anybody has any trial about this?