VCS2016 cannot compile ok

[luoyanghero]

My OS env is CentOS7.5; vcs version is L-2016.06;
gcc version is "gcc version 4.8.5 20150623 (Red Hat 4.8.5-28) (GCC) "

I use a synopsys lab for vcs env test.
First run, it show me need add env 'setenv VCS_ARCH_OVERRIDE linux '

Then I added and try rerun. It should show me 'Simv generation successfully completed' when compile ok.
still failed, I try to run './simv', not ok.
I confirmed my synopsys license file, there have added vcs feature.
Is there anybody meet this?

The following is my excute log and vcs lab contents.

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###=================================
[luoy@tteda parta]$ vcs add4.v add8.v addertb.v fa.v 
 
Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS Linux release 7.5.1804 (Core) ' is not supported on 
  'x86_64' officially, assuming linux compatibility by default. Set 
  VCS_ARCH_OVERRIDE to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.
 
                         Chronologic VCS (TM)
            Version L-2016.06 -- Mon May 18 17:12:29 2020
               Copyright (c) 1991-2016 by Synopsys Inc.
                         ALL RIGHTS RESERVED
 
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
###=================================
 
###=================================
[luoy@tteda parta]$ ./run.csh 
         ##################################
            Welcome TongTu eda server! 
####################################################
                         Chronologic VCS (TM)
            Version L-2016.06 -- Mon May 18 17:15:03 2020
               Copyright (c) 1991-2016 by Synopsys Inc.
                         ALL RIGHTS RESERVED
 
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
 
Parsing design file 'add4.v'
Parsing design file 'add8.v'
Parsing design file 'addertb.v'
Parsing design file 'fa.v'
Top Level Modules:
       addertb
No TimeScale specified
Starting vcs inline pass...
 
1 unique modules to generate
1 module and 0 UDP read. 
recompiling module addertb
All of 1 modules done
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv   -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  -m32 -m32 -rdynamic   amcQwB.o objs/amcQw_d.o   _15885_archive_1.so  SIM_l.o       rmapats_mop.o rmapats.o rmar.o  rmar_llvm_0_1.o rmar_llvm_0_0.o          /eda/s/vcs-mx/L-2016.06/linux/lib/libzerosoft_rt_stubs.so /eda/s/vcs-mx/L-2016.06/linux/lib/libvirsim.so /eda/s/vcs-mx/L-2016.06/linux/lib/liberrorinf.so /eda/s/vcs-mx/L-2016.06/linux/lib/libsnpsmalloc.so    /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so /eda/s/vcs-mx/L-2016.06/linux/lib/libsimprofile.so /eda/s/vcs-mx/L-2016.06/linux/lib/libuclinative.so   -Wl,-whole-archive /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsucli.so -Wl,-no-whole-archive          /eda/s/vcs-mx/L-2016.06/linux/lib/vcs_save_restore_new.o /eda/s/vcs-mx/L-2016.06/linux/lib/ctype-stubs_32.a -ldl  -lc -lm -lpthread -ldl 
../simv up to date
CPU time: .186 seconds to compile + .301 seconds to elab + .244 seconds to link
[luoy@tteda parta]$ ls
add4.v  add8.v  addertb.v  clean.csh  csrc  fa.v  run.csh  simv  simv.daidir
[luoy@tteda parta]$ simv
simv: Command not found.
 
###=================================
[luoy@tteda parta]$ ./simv
Command line: ./simv
 
--- Stack trace follows:
 
Dumping VCS Annotated Stack:
#0  0xf7794430 in __kernel_vsyscall ()
#1  0xf2a481cb in waitpid () from /lib/libc.so.6
#2  0xf29c8ace in do_system () from /lib/libc.so.6
#3  0xf29c8ed5 in system () from /lib/libc.so.6
#4  0xf2c91e2b in system () from /lib/libpthread.so.0
#5  0xf72363ac in SNPSle_10ee25eff68cd8461c9146fa1d0b35e87067f3c8015b313e639d2928478c79b3f673f99203bcf8be64600612100082236bffb2007f1e0ef9 () from /eda/s/vcs-mx/L-2016.06/linux/lib/liberrorinf.so
#6  0xf723783c in SNPSle_10ee25eff68cd8461c9146fa1d0b35e87067f3c8015b313efba706aab251478fa49e66610e453774633a6c152e7ef778f2202cda681f3d4e () from /eda/s/vcs-mx/L-2016.06/linux/lib/liberrorinf.so
#7  0xf722ffe1 in SNPSle_d35ca1ff70d465c2b9b1a72eee90a506fdd009d3de3db1de () from /eda/s/vcs-mx/L-2016.06/linux/lib/liberrorinf.so
#8  0xf5015b70 in SNPSle_64133461705005bb725549e2e6fa1b3f () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#9  0xf4e91365 in SNPSle_82244d58c54c18c70d63edc9becab634 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#11 0xf71fa90d in mem_free () from /eda/s/vcs-mx/L-2016.06/linux/lib/libsnpsmalloc.so
#12 0xf71e5406 in snpsFreeFunc () from /eda/s/vcs-mx/L-2016.06/linux/lib/libsnpsmalloc.so
#13 0xf4ca8171 in SNPSle_77e776236473f4bc83d28b2811172395 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#14 0xf4ca2d4d in SNPSle_4e2b4bf1677349c165275718f4085a72 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#15 0xf4b52cec in SNPSle_e08561af70b15158c1effee38014f2e6 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#16 0xf4b52e43 in SNPSle_6a600e65c1e59889d2167a3056e08869 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#17 0xf4b52ea3 in SNPSle_79019f86c02f3a7a4fc861b56b22e07a449f142e33a64a009cd88060dca82713b97bc310751f5b0c () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#18 0xf2c89b3c in start_thread () from /lib/libpthread.so.0
#19 0xf2a8844e in clone () from /lib/libc.so.6
#0  0xf7794430 in __kernel_vsyscall ()
#1  0xf2a48676 in nanosleep () from /lib/libc.so.6
#2  0xf2a4844d in sleep () from /lib/libc.so.6
#3  0xf4ad5c27 in SNPSle_95ae9cc2e78cc668673c60b8d88c4908 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#4  0xf4ad5dea in SNPSle_92de4d0d4cf0d6931bc37e8d42a01d93 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#5  0xf4ad44e6 in SNPSle_b76ef993ee82b3d58a5cadddbec8b67c () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#6  0xf4ad47ee in SNPSle_f28f24b8c84ac8f6e02e0b03bcd33aa8 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#7  0xf4aa02b0 in SNPSle_b02289328df49303de0a4a986839ba718c1b162de585ec41 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#8  0xf4aa0ee5 in SNPSle_b02289328df493035a8cfe7a2a96e3f1 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#9  0xf4aa2ea1 in SNPSle_7309f02bf869c35a32837a6e487da0db () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#10 0xf4aa3b41 in SNPSle_b02289328df493035a8cfe7a2a96e3f14356a2494eb82428 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#11 0xf4aa512d in SNPSle_b02289328df493035a8cfe7a2a96e3f105a2510afcb822b0f2351f16fde66779 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#12 0xf4aa5a7a in SNPSle_ba11b1edbd04051f5bb81b1861cdf84a () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#13 0xf4a919af in SNPSle_2e65c0794628fc5af60953149776c29b () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#14 0xf4a87ed6 in SNPSle_541f757be362289a7c9e5618c0ff28327846f8d3cc02839f () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#15 0xf4a87001 in SNPSle_541f757be362289a7c9e5618c0ff283244765933a2ab0071 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#16 0xf4a80644 in SNPSle_c0de1345d5ab80930e06dd2b68f214c3 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#17 0xf4a81883 in SNPSle_25cd5712eacded5feaee03dc3430943e () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#18 0xf502e85b in SNPSle_490598bfebcc8e8183ad3550288b1f82 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#19 0xf503a178 in SNPSle_490598bfebcc8e81 () from /eda/s/vcs-mx/L-2016.06/linux/lib/libvcsnew.so
#20 0x0804cc63 in main ()
No context available
[luoy@tteda parta]$ ls

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The following is the lib guide contents:

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###=================================
 
Getting Started
You will be using the following carry-select 8-bit adder for this lab:
Figure 1-1: 8-bit Carry Select Adder Block Diagram
Our goal is to use this simple design to take you through the fundamentals of the two-step VCS simulation process.  This lab is divided into three parts.  Each part has its own associated tasks. Here's a preview of what you will be doing:
?   Compile the adder Verilog source files to generate a simulation executable.
?   Simulate the 8-bit adder by executing the simulation executable.
?   Interpret the simulation results displayed on console to determine whether or not the 8-bit adder is working correctly.
?   In Part A, all the Verilog source files for the 8-bit adder reside in the working directory.
?   In Part B, some of the Verilog source files for the 8-bit adder are in the working directory, and the rest are in a library directory. You will compile them and then use a compile-time file to simplify the VCS compile command line typing.
Figure 1-2: Flow Diagram of Lab Exercise
Part A:  The two-step Simulation Process
Task 1  Compile to Generate Simulation Executable
In Part A of the lab1, all the Verilog source files for the 8-bit carry select adder reside in your lab working directory.
After logging on to the workstation, go into the lab1 Part A directory.
1.  shell> cd vcs/lab1/parta
You should see four files: fa.v, add4.v, add8.v, and addertb.v.
2.  shell> ls
fa.v, add4.v and add8.v are the Verilog source files for the blocks shown in Figure 1-1.  addertb.v is the testbench used to check the funtionality of the adder.
Compile the Verilog files and generate the simv simulation binary executatble.
3.  shell> vcs addertb.v fa.v add4.v add8.v
When the compilation is done, you should see the message
Simv generation successfully completed
Task 2  Run Simulation
Run the testbench and simulate the design by executing simv.
1.  shell> simv
When the simulation is done, you should see the message
$finish at simulation time           13107200
      V C S   S i m u l a t i o n   R e p o r t
Time: 13107200
CPU Time:  0.490 seconds; Data structure size: 0.0 Mb
Mon May 22 09:58:26 2000
(Note:  your date & time will be different)
Indicating that the simulation has completed.  The CPU time used and the memory used during the simulation are also reported.
Task 3  Check Simulation Results
You should also see the following printout generated by Verilog system task calls embedded in the testbench.
?
*** Testbench Successfully completed! ***
?
This verification run was successful!  In Lab 2 we will see how to generate messages to help us debug code errors.
Task 4  Create Simulation Executable with Different Name
The VCS default simulation executable file name is simv.  You can direct VCS to generate a different executable name by using the ?o switch.
Recompile the adder design, this time, generate a simulation executable called addertest.  
Compile the Verilog files and generate the simv simulation binary executatble.  (please note that the switch is the letter ?o? not the number ?0?)
1.  shell> vcs addertb.v fa.v add4.v add8.v ?o addertest
Check the content of the parta directory.
2.  shell> ls
You should see 6 files including the simulation binary executable addertest.
Execute this simulation binary to make sure that the simulation results remain the same.
3.  shell> addertest
You should once again, see the following print out generated by the testbench.
?
*** Testbench Successfully completed! ***
$finish at simulation time           13107200
      V C S   S i m u l a t i o n   R e p o r t
Time: 13107200
CPU Time:  0.490 seconds; Data structure size: 0.0 Mb
Mon May 22 10:08:21 2000
?
Part B:  Working with Library Directories
Task 1  Compile & Simulate using Design Library Directory
In Part B of the lab1, we have moved fa.v and add4.v into a library directory.  The new file directory structure now looks like the following:
The fa.v and add4.v modules are now modules within the library directory lib.
Go to lab1 Part B working directory.
1.  shell> cd ../partb
2.  shell> ls
You now should only see two files: add8.v, and addertb.v.
Compile the design again.  Only, this time, we need to reference the library directory file.
You will also use the ?R switch as a shorthand to execute simulation immediately after compilation.
3.  shell> vcs addertb.v add8.v ?y ../../lib +libext+.v -R
Notice that because our library files have the .v extension, the +libext switch is required to get vcs to search the .v extension files.
The source file contents have not changed, only the physical placement of the file has changed, you should see identical simulation results as in part A.
Task 2  Compiling with ?f File Switch
Simplify the command line entry by using the ?f compile-time switch.  First create a file which contains the names of all the source files or libraries for the design.  When compiling the design, reference this file with the ?f switch.
1.  Use any editor you are comfortable with and create the file ?adder.f? containing the following:
addertb.v
add8.v
-y ../../lib +libext+.v
Compile and simulate the design by using the ?f switch as follows:
2.  shell> vcs ?f adder.f -R
The source file contents have not changed, only the physical placement of the file has changed, you should see identical simulation results as in part A and part B.
You are done!  Compilation and simluation using VCS is very simple.
 
Try out some of what you?ve learned by answering the following questions.
Can you embed the ?R switch in the adder.f file?    
Can you use the ?v switch instead of the ?y switch?  How?

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My run.csh contents is

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###=================================
#!/usr/bin/env csh
vcs addertb.v fa.v add4.v add8.v
./simv
 
addertb.v
###=================================
module addertb;
reg [7:0] a_test, b_test;
wire [7:0] sum_test;
reg cin_test;
wire cout_test;
reg [17:0] test;
 
add8 u1(a_test, b_test, cin_test, sum_test, cout_test);
 
initial
begin
  for (test = 0; test <= 18'h1ffff; test = test +1) begin
    cin_test = test[16];
    a_test = test[15:8];
    b_test = test[7:0];
    #50;
    if ({cout_test, sum_test} !== (a_test + b_test + cin_test)) begin
      $display("***ERROR at time = %0d ***", $time);
      $display("a = %h, b = %h, sum = %h;  cin = %h, cout = %h",
               a_test, b_test, sum_test, cin_test, cout_test);
      $finish;
    end
    #50;
  end
  $display("*** Testbench Successfully completed! ***");
  $finish;
end
 
 
 
 
    
endmodule
 
add4.v
###=================================
module add4(a, b, cin, sum, cout);
input [3:0] a, b;
input cin;
output cout;
output [3:0] sum;
wire [3:1] c;
 
fa u1(a[0], b[0], cin, sum[0], c[1]);
fa u2(a[1], b[1], c[1], sum[1], c[2]);
fa u3(a[2], b[2], c[2], sum[2], c[3]);
fa u4(a[3], b[3], c[3], sum[3], cout);
 
endmodule
 
add8.v
###=================================
module add8(a, b, cin, sum, cout);
input [7:0] a, b;
input cin;
output cout;
output [7:0] sum;
wire c4, c8_0, c8_1;
wire [7:4] sum_0, sum_1;
 
add4 u1(a[3:0], b[3:0], cin, sum[3:0], c4);
add4 low_add(a[7:4], b[7:4], 1'b0, sum_0, c8_0);
add4 high_add(a[7:4], b[7:4], 1'b1, sum_1, c8_1);
 
assign sum[7:4] = c4?sum_1:sum_0;
assign cout = c4?c8_1:c8_0;
 
endmodule
 
fa.v
###=================================
module fa(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
assign {cout, sum} = a + b + cin;
endmodule

---