Hi dear all,
I have a design. I synthesized it Synplify Premier for Xilinx Virtex 4 fpga device. I could perform behavioral simulation and post synthesis simulation with VCS simulator. Synplify Premier uses Place&Route tool of Xilinx for place and route job. It places and routes without any problem. When I want to perform Post Place and Route simulation with VCS, it asks for "Post Place and Route Netlist". When I had a look at implementation result files all the files I can see with "netlist" label are edif netlist, srd netlist, srm netlist, srl netlist. I tried to give each of them as an input, but it didnt accept. I have been reading documents from Synopsys, have been searching on forums, websites. But couldnt find any solution. Does anybody have any experience with such problems/issues? Using Synplify Premier and VCS together? Btw, I give Post Place&Route Simulation Netlist input file using a gui, and it wants me to give post p&r netlist in vhd format but no file with vhd or vhdl is created after all steps of synthesis, map, place and route. I dont really know what to do.