VCS Mixed Simulation VCS VHDL Verilog Mixed language simulation with UVM

[Kashif Minhas]

This is to state that I am currently working on Mixed-Design (Containing VHDL && Verilog Files) Verification using SVerilog/UVM Testbench.

After building the initial verification environment when I compile the design & TB files together through Makefile script it gives an error that TB top is not able to find the Design instantiation. My design includes a VHDL top with a Verilog file instantiated in it.

I make separate flist files for Verilog VHDL & SVerilog files.

My Makefile commands are mentioned below:

vlogan -work work +v2k +incdir+$(UVM_HOME) $(UVM_HOME)/uvm_pkg.sv +libext+.sv -f ./results/vlog_flist.f -ntb_opts uvm-1.2 -full64 -debug_all

vhdlan -work work -f ./results/vhdl_flist.f

vcs -timescale=1ns/1ps -f ./results/build_uvc.f -error=noZONMCM -ntb_opts uvm-1.2 -sverilog -cm line+cond+tgl+fsm -ova_cov -cm_hier config_covg.cfg -cm_name ${TEST} -LDFLAGS -Wl,--no-as-needed -debug_all

cd ./results

cd ./results && mkdir -p $(TEST)_build/SEED_$(SEED)

mv -f csrc* simv* ./results/$(TEST)_build/SEED_$(SEED)/

cd ./results/$(TEST)_build/SEED_$(SEED) && ./simv +UVM_TESTNAME=${TEST} -cm line+cond+tgl+fsm +UVM_TIMEOUT=${TIME_OUT} ->log_${TEST}_build.log

 

[dpaul]

@Kashif Minhas
Can you not just compile your design containing the top-level VHDL and Verilog sub-modules?
In that way you can test what is wrong, some path issue or files not present, etc!

 

[Kashif Minhas]

Parsing of Verilog file is done first followed by VHDL top and other files through commands vlogan & vhdlan in directories AN.DB & 64 respectively. But while parsing testbench top module through vcs command in Makefile it gives an error that instantiated design is not found in top.

 

[dpaul]

I understood what you did! I wanted to guide you through some usual debug steps...

What I meant is, did you get any compilation errors when compiling your design hierarchy?
Are you setting the compile order correctly (the top-module must be compiled last)?
Did you double-check the file paths inside your Makefile?

 

[Kashif Minhas]

Yes the design is compiled without any errors.

The verilog sub-module of VHDL design top is compiled using the following command located in vlog_flist.f flist.
vlogan -work work +v2k +incdir+$(UVM_HOME) $(UVM_HOME)/uvm_pkg.sv +libext+.sv -f ./results/vlog_flist.f -ntb_opts uvm-1.2 -full64 -debug_all -l

While the other Design VHDL files are placed in vhdl_flist.f flist
vhdlan -work work -f ./results/vhdl_flist.f

But when elaboration command is run having testbench files in build_uvc.f flist then vcs gives error that the module not found on design instantiation.

vcs -timescale=1ns/1ps -f ./results/build_uvc.f -error=noZONMCM -ntb_opts uvm-1.2 -sverilog -cm line+cond+tgl+fsm -ova_cov -cm_hier config_covg.cfg -cm_name ${TEST} -LDFLAGS -Wl,--no-as-needed -debug_all

 

[Kashif Minhas]

I could not understand how the testbench top will know where the compiled VHDL design is located or where to get the compiled design from because design is compiled in the project directory in folder named 64.

 

[Kashif Minhas]

I am trying to verify a simple VHDL based adder design using UVM Testbench in VCS.

My Makefile Commands are below:
vhdlan -work work -f hdl_flist.f
vlogan -work work +v2k +incdir+$(UVM_HOME) $(UVM_HOME)/uvm_pkg.sv +libext+.sv -f tb_flist.f -ntb_opts uvm-1.2 -top adder_tb -full64 -debug_all
vcs -timescale=1ns/1ps -top top -ntb_opts uvm-1.2 -full64 -LDFLAGS -Wl,--no-as-needed +UVM_TESTNAME=${TEST} -full64

First I compile my adder design file through vhdlan and then my tb files through vlogan command. But at vcs elaboration command the error occurs that "The design Entity/Module not found in the following liblist"? I cross verify all my testbench connections and all are ok. But still the error occurred.