Ranand
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Hi ,
I have an encrypted RTL (encrypted using the synopsys Public key and cadence ncprotect utility.
But when trying to compile the protected file ,I get the following error,
Can somebody please help me as to what this issue is and how to fix it ?
Thanks,
Ranand
- - - Updated - - -
Hi,
This error seems to be because of the VCS tool not able to understand that the Verilog file is a protected rtl.
Is there any additional switches /commands that need to be used in VCS for compiling and simulation a protected RTL(from cadence ncprotect)?
Thanks,
Ranand
I have an encrypted RTL (encrypted using the synopsys Public key and cadence ncprotect utility.
But when trying to compile the protected file ,I get the following error,
Code:
Warning-[USCLA] Unterminated string
Unterminated string found in file 'adder_aec.vp'
at line '9'
for an argument 'IST"
`pragma protect data_method="aes128-cbc"
`pragma protect key_keyowner="Synopsys"
`pragma protect key_keyname="SNPS-VCS-RSA-1"
`pragma protect key_method="RSA"
`pragma protect encoding = (enctype = "base64", line_length = 76, bytes =
128)
`pragma protect key_block
E41jdrb++LtjB/eGeO9+eJUQTr3iS9mVRI95hc7/DIiLbNlQCMNjS/cZPuplgY1GexKS0t7gDDLI
1vWVoLnvB94absLmdbdZRNPfS9hsfg7n3muzSdlAERrgdfan17QUatRJx5YrYvdRr/f9gwuKi5jj
8O8TeDMYtgxxhq7h7Rw=
`pragma protect encoding = (enctype = "base64", line_length = 76, bytes =
256)
`pragma protect data_block
lujf2DVPsigDbuCJ6LzygtrJHOBsPkZnTUTpgUX/sRwtf5Xrz9IXlFfFnqm+a48hp9/u9aLmn3W4
9d1Pn7qqPZDBNt1WTc9LGMKbjkQTNrLCC/P32M7j8aBbMvp/my3mQL3/zeWLGTASS3Fhoy5HZy5/
moMlBsvBVBy4cTZLfF7e008ohDhst6xjw/PfV0hTFAcDGft5L5QJQbPaEky9uU4Q+yb+e6H+x6k0
FIIp32engPz0afBGP80vynP/blYl+u9f7BFB4KnDOv1omHdAAv9FGarlp9h6q31YENfZYpL8L1tv
aer4+Nj1XENIVHUTKJyMbpa1eMDby+pSymPerQ==
`pragma protect end_protected
endmodule
'.
Error-[SFCOR] Source file cannot be opened
Source file "module" cannot be opened for reading due to 'No such file or
directory'.
Please fix above issue and compile again.Can somebody please help me as to what this issue is and how to fix it ?
Thanks,
Ranand
- - - Updated - - -
Hi,
This error seems to be because of the VCS tool not able to understand that the Verilog file is a protected rtl.
Is there any additional switches /commands that need to be used in VCS for compiling and simulation a protected RTL(from cadence ncprotect)?
Thanks,
Ranand