VCO pulling effect and S-parameter

vco pulling

Hi all,
Would you give me any hints about the following questions:

1) If I know the s-parameter of a block(such as a buffer amplifier), how to calculate the input impedance and output imdedance according to S11,S12,S21 and S22?

2) Many papers mentioned that VCO's pulling effect is due to the varying load.I am puzzled why the load impedance will vary if the VCO is fixed to a mixer or a divider in PLL?

Thank you very much.

pulling effect

The input impedance expression of a 2 port can be derived to be as follows:

Zin = Zo * [(1 + S11)(1-ρl S22) + S12 S21 ρl] / [(1-S11)(1-ρl S22) - S12 S21 ρl]

where Zo is the characteristic impedance of the S parameters
ρl is the reflection coefficient of the load = [Zl - Zo]/[Zl+Zo] where Zl is the load impedance

The VCO load changes in if the output of the PLL which is the VCO is connected to something, and if there is not buffer before that output is taken so the load of the VCO can change.

zl sparameter

To aryajur
Thank you very much for your reply.

In my design, the PLL output signal is NOT from VCO directly but from the divider's output(i.e. from PFD's input).So I think the VCO's load impedance is a constant. But I am not sure whether the following two cases will be the same?

1) The VCO is directly connected to divider without a buffer amplifier and load impedance is a constant, for example,it is Z1=R1+j*X1(here X1 means the L&C impedance from divider's packaging model. For VCO is connected to a mos gate,so the R1 is very large, for example 10000ohm).

2) The VCO is connected with a buffer, then the buffer is connected to a divider. It is sure that the VCO's load impedance is a constant Z2=R2+j*X2. (R1≠R2 and X1≠X2)

I don't know whether these two cases both avoid "pulling effect"?
i.e., Is it right: Only varying load will produce "pulling effect", a constant load(whether Z1 or Z2) will NOT produce "pulling effect"?

Thank you!

pulling vco

Hmm, well I was hoping you wouldn't ask for the derivation, since I am too lazy to write it down
But ok, I will try writing down here:

If we take the general 2 port model with I1 going in port 1 and I2 going in port 2. V1 applied across port 1 and V2 applied across port 2, with positive terminals so that they reinforce I1 and I2. Now we can define input impedance as:

Zin = V1/I1, with all independent sources set to 0, i.e. V2 = 0 but its impedance will still remain, to account for the general case. So the 2 port model to calculate the impedance is, V1 (ideal) still connected with I1 flowing in port 1 and a load impedance Zl connected to port 2.

Now we know for port 1:
V1 = V1i + Vir
I1 = I1i - I1r

where i and r denote the incident and reflected components of the voltage and current waves.

so Zin = (V1i + V1r)/(I1i - I1r)

The scatterring parameter equations are:

b1 = S11 a1 + S12 a2 ..............(1)
b2 = S21 a1 + S22 a2 ..............(2)

where ak = Vki / √Zo = Iki √Zo = root of incident power on port k
bk = Vkr/ √Zo = Ikr √Zo = root of reflected power from port k

where Zo is the characteristic impedance used to characterize the scatterring parameters.

so Zin = Zo (a1 + b1)/(a1 - b1) = Zo (1 + b1/a1) / (1 - b1/a1)

SO now you just need to find b1/a1 from the scatterring parameter equations (1) and (2)

For the load impedance Zl, the incident power is the power that is reflected from port 2 = b2² and the reflected power from Zl is the power that is incident on port 2. So the reflection coefficient of the Load can be defined as:

ρl = a2 / b2

Now put this in (2) we get:

a2 = ρl S21 / ( 1 - ρl S22)

Put this in (1) to get b1/a1 and put that ratio in the expression for Zin to get the Zin expression I gave below.
So everything reverse for Zout, in fact you can just get it from Zin by replacing ρl by ρs and intercahnging 1 with 2 in the Zin expression.
Hope this made things clear.

pll vco load pulling

aryajur
Thank you for your "lazy"...!!

I just post a new reply on "pulling effect" as following:

=======
In my design, the PLL output signal is NOT from VCO directly but from the divider's output(i.e. from PFD's input).So I think the VCO's load impedance is a constant. But I am not sure whether the following two cases will be the same?

1) The VCO is directly connected to divider without a buffer amplifier and load impedance is a constant, for example,it is Z1=R1+j*X1(here X1 means the L&C impedance from divider's packaging model. For VCO is connected to a mos gate,so the R1 is very large, for example 10000ohm).

2) The VCO is connected with a buffer, then the buffer is connected to a divider. It is sure that the VCO's load impedance is a constant Z2=R2+j*X2. (R1≠R2 and X1≠X2)

I don't know whether these two cases both avoid "pulling effect"?
i.e., Is it right: Only varying load will produce "pulling effect", a constant load(whether Z1 or Z2) will NOT produce "pulling effect"?

vco s parameter

hi trashbox,
The output of divider should be locked to the reference frequency. Then what is the usage of your PLL?

vco s-parameters

Hi vale!
My PLL is as following(core configuration):
VCO(2GHz)-->Div2(1GHz)-->Div5(200MHz)-->....-->PFD

Then I will connect the Div2's output(1GHz) to many other dividers(such as /1,/2,/3,/4,/6 etc),these outputs of the dividers are my PLL outputs.

vale said:

hi trashbox,
The output of divider should be locked to the reference frequency. Then what is the usage of your PLL?

Click to expand...

vco s11

hi trashbox,
did ur PLL work as a frequency synthesizer with constant reference clock ?
if it was, then the pulling effect should only occur before the lock of PLL, after lock the VCO should be constant frequency, so there is no more "pulling".