VCO frequency and area

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hanikapa

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Hello,
I have a basic question about LC-oscillators. I will consider a case that the sampling clock of 1GHz is needed. Since the inductors get large area on chip, what is the trade offs that I use a 8GHz VCO and divide it by 8 instead of using a 1GHz VCO?
Thanks
 

hanikapa said:
Since the inductors get large area on chip,
what is the trade offs that I use a 8GHz VCO and divide it by 8 instead of using a 1GHz VCO?
Click to expand...
You have to consider power consumption rather than occupied area.

Regarding area, direct 1GHz VCO require too large inductor.
Generally, 2GHz VCO or 4GHz VCO is used.
 
So by increasing the vco frequency, the power also increases?
 

hanikapa said:
So by increasing the vco frequency, the power also increases?
Click to expand...

Sure: every rising and falling edge costs a certain amount of energy [V*I*Δt = Ws]. Assuming similar structures, if you double the frequency, you double the number of energy packages per time, i.e. power [Ws/s = W].
 
hanikapa said:
So by increasing the vco frequency, the power also increases?
Click to expand...

If you talk about the Power Consumption, there isn't any linear relationship between Power Consumption and Frequency of Oscillation.It totally depends on Gm value that plays important role in oscillator design.
The exact reason of building Higher Frequency VCOs is to shrink the occupied are on the silicon.
 
hanikapa said:
So by increasing the vco frequency, the power also increases?
Click to expand...
Negative impedance value of VCO core is roughly equial to -gm/(2*pi*freq*C).
As freq increase, negative impedance value decrease, so you have to increase gm.

Also power consumption of frequency divider is fairly large if you divide 8GHz.

And see www.edaboard.com/showthread.php?t=342858
 

Negative Resistance value will be Re{Zin}=-2/gm for both Bipolar and MOS Cross-Coupled VCO Structures.
 

BigBoss said:
Negative Resistance value will be Re{Zin}=-2/gm
for both Bipolar and MOS Cross-Coupled VCO Structures.
Click to expand...
Correct.
I showed wrong equations.

Assume series resistance of inductor as Rs.
And assume circuit loss is zero.

Gm must be larger than Rs*(2*pi*freq_res_p*Cp)^2.
As freq increase, necessary negative impedance value also increase, so you have to increase gm.
 

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hanikapa said:
Since the inductors get large area on chip
Click to expand...

Oscillator phase noise depends on inductor Q factor. When maximizing the inductor Q factor, it often helps to use less turns, which then requires larger diameter for the same L value. But of course, you can use more turns, resulting in smaller area, if lower inductor Q is still acceptable.
 

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