VCD to ATE vector conversion

[sparso]

I need to write a script to convert VCD/EVCD/LSI files to ATE format(Teradyne/Verigy) - Can anyone help me to get started with this?

How do I go about starting this task? I do not and will not have access to ANY commercial softwares. I will have to write is all my self.

Thank you very much.

 

[varun]

Hello Sparso ,

You can check with the ATE vendors , or you can refer to vector Translations tools from
Simutest , tool --> Verifier

 

[sparso]

Varun,

Please read my post again ...I said "I need to do it
myself and I will not have access to any software
that cost money" so your suggestions are useless.
Please try to reply if you have any thing to contribute.
You seem to have zero knowledge on this matter.

 

[zigzagfish]

Hi sparso, for Verigy, they have a tool called ASCII Inteface, which can help to convertion. But you still need to convert your own vcd tool to some intermediate tool which can be viewed by ASCII Interface

 

[sparso]

so zigzagfish,

How is your answer relevant to my question?
Please read my reply to varun. Try to contribute to the
original question or don't reply!

 

[veejaye]

sparso,

I don't know if u have already started working on it. I was searching for a relevant stuff and came across the discussion.

First thing is you got to know is how to parse the VCD file?. Anything that starts with a $var will have the Pin names whose transition are dumped. So u got to extract the pinlist out of it. And each pin has an associated symbol.
for ex:
$var wire 1 ! cs $end

I believe here the pin name is cs which is single bit and the associated symbol is '!'.
when u move further down the VCD file
#16600
1!
#1800000
0!
anything that comes after # is time in fs.
1! means the pin associated with the symbol ! moves to state 1 at the above time.

Based on this you will have the full info about a particular pin.

Now to convert to tester understandable format u got to fix the cycletime.
let us say that u have fixed the cycle time as 100ns. the u have to divide the entire simulation time by the cycletime. This will give the number of test cycles. After that you have to find all the transitions that happen inside the first cycle, second cycle and so on.

Then u have to fix the launch time for the inputs and strobe time for the outputs relative to the cycle time.
Now u will have info on the pin list and the cycle at which different pins toggle.

The following are the inputs u need before u start the conversion.
cycletime
start & end time (optional) u can assume start as 0 and end as end of simulation.
input and output definition of the pins. Note that u won't get this info from the VCD.
launch time for the inputs. usually 10% of cycletime after cycle start.
strobe window for the output. usually 90% to 95% of cycle time
for a 100ns cycletime the launch will be 10 ns and the strobe will be 90 to 95ns.

Now u got to identify ur target tester. If it is verigy agilent93k u need to understand the .vec file syntax.

I don't have any idea about that. If it is Credance vista tester i will be able to help u in understanding the .vec syntax, the timesets and the wavesets.

I am getting bored of typing........

-VJ.