VCC depends on layer stackup??

[kabaleevisu]

Hi all

In my schematic the following VCC is using 9v, 5V , 3.3V 2.5V, 1.8 V. but i could not identify how to design it .i though is it possible to design in four layer?? (till now i am design the board in 2 layer ). whether layer stack up increases depends on VCC or no of nets??

Note: how to identify the perticular schematic design in 4 layer and 6 layer and so on....

why we go for high speed design??

please help anyone.

 

[logicon]

Conventionally, stack up would be a natural cause with its consequential increase in cost. If you are restricted to double layer, I would suggest zoning your board or grouping your components (whichever is convenient).
Concerning your schematic, you may want to consider identifying each of these differently on your net assignment and labeling those nets as POWER . Hope it helps

 

[marce]

with that many voltages your gonna have fun. I would presume you have some sort of FPGA, CPLD or processor, with different core voltages?
Are there BGA devices?
What are the signal speeds and rise times?
What is the decoupling scheme for the various supplies?

 

[Mattylad]

You could always have a single 9v plane and have local power supplies for each section.

However I am sure that murpheys law says that the components will all be at separate ends of the board using the same voltage.

This could be a heck of a split plane

 

[marce]

Its pretty much standard for high density designs, by the time you add 'pi-filtered' sub supplies you can have up to 22 seperate supplies to consider on a board. I amd doing one now with; 22 seperate supllies over 3 power layers, each layer closely coupled with a gnd layer (0.1mm max apart) to help reduce simultaneous switching noise. Due to the complexity of the components BGA, QFN etc and the decoupling requirements, and for both signal and power delivery integrity you need to realy use planes.
When labelling power on a schematic the reccomended format is + or - then the voltage, then any extra identifiers:
+3V3
+1v2_CORE
-12V
etc

 

[kabaleevisu]

hi marce
thanks for your reply. this board is depends on FPGA design. i need clear suggestion form you i like to design this board in four layer.how to design it???
NOTE:layer increases depends on number of net in schematic or VCC or board size??

 

[marce]

https://www.mentor.com/products/pcb...b-system-design/techpubs/requestpubs&id=52590

Download this guide.
Will reply in detail ASAP.

 

[marce]

Finding the correct number of layers for any design is a compromise, as is all PCB design, but with FPGA's, multiple supply voltages and high speed becomes more of a problem. There are a number of factors that determine the number of layers as follow:
1. BGA's; the first determining factor, route breakout determines the base number of layers when using BGA's. The book BGA breakout by C. Pfeil explains this in more detail. But depending on your track and gap, and via size will give you the minimum number of layers required to break out of a BGA device.
2. Power requirements; how many voltages are there, and how are they distributed. I highlight all the separate supply voltages in different colours so I can determine how to get the right voltages to the right pins. This will determine how many power layers are required. Generally each power layer will also require 0V (GND) layer, closely coupled (i.e. 0.1mm max pre-preg between these layers during manufacture) to provide sufficient plane capacitance to help signal integrity and EMC. This plane capacitance is the first line of defence against ground bounce, the de-coupling capacitors being the next in line, depending on their value and stray inductances.
3. Signal Integrity; again depending on the signal speeds, rise time etc there may be signal integrity issues, the signal may have to be of a certain impedance. This requires the signals to be closely coupled to a 0V (GND) plane, again complicating the layer stack up. The characteristic impedance of routes is best determined in conjunction with your PCB fabricator; they use a program called Polar to determine impedances etc and will give you feed back on your stack up and any recommendations to achieve the desired results.
4. Cost; all the above requirements have to be balanced up against the expected cost of the product, adding layers puts the complexity of the board up and thus increases cost, thus depending on how cost sensitive a design is determines the compromises of the above to meet the expected cost of the board.
There are other issues, but the above cover some of the main issues with determining how many (and off what type, signal, power, gnd) layers you will require for a particular PCB design. It can be complex due to so many factors affecting the decisions.
Hope this helps, though I suspect it may raise more questions.
Marc

 

[kabaleevisu]

hi marco
thanks for your reply

 

[marce]

I hope it helps, if you have any more questions I will always try to help, or have a pointer to some relevant info. I tend to collect quite a lot of info on PCB design. One other reccomendation I will make is sign up for the digital copy of "Printed Circuit Design and Fabrication" an excellent source of design tips etc.
Marc