Varying Verilog code simulation results in "Xilinx Vivado" compared to "Xilinx ISE"

Hello there,

I wrote Verilog code for implementing "LPC protocol"(Low Pin Count Protocol) driver. And this code works fine in simulation. There was "LPC Host" which sends data over a 4-bit LAD bus and signals Reset and LFRAME (start of LPC frame - cycle) and "LPC Peripheral" which is connected to Host. First I have only I/O cycles support in the project and on simulation (test bench brings "LPC Host" and "LPC Peripheral" to life) and it works fine. Now I want to check if "LPC Peripheral" ignores other cycle types (eg Memory R? W, DMA, etc.). For this purpose, I implemented additional support for "Memory R / W" cycles in "LPC Host" without changing "LPC Peripheral". I also made the required changes to the test bench.
Now I come to the heart of my problem: "When I simulate Verilog code in "Xilinx Vivado 2019.1" the results are perfectly correct (as expected), but if I simulate the same code in Xilinx ISE - the results are very different and incorrect."
I checked also a simulation of this code in an open-source Verilog simulator called "Icarus Verilog" (see link: Icarus Verilog), and the results also were bad and similar to those in "Xilinx ISE".
Could someone more experienced explain to me what could be the reason for this behavior of the simulation? I am not sure if my design is working properly and checking on the FPGA kit, in this case, can be difficult for several reasons.
I attached source files of my project (in zipped archive)
1) lpc_host.v
2) lpc_periph
3) lpc_defines.v (constants used in the design)
4) lpc_periph_tb.v (this is test bench)

Thanks in advance and Regards

Hello,

BTW: I am asking out of curiosity: has anyone encountered such a case where simulating the same code in different environments gave different results?

Best Regards

Hi,

no one has encountered such a situation and can not help. Maybe at least some hints or guesses.

Best Regards