Variation in the current with technology change

[Sambhav_1]

Hi,
I am comparing the two technology nodes,the new one is the fast devices version, and the devices in the new node are faster,i.e Id has increased and vt has reduced.but when i am comparing the simulation results(Mixed signal circuit, only inverters and level shifter are there), then current from VDD has been reduced significantly,however acc. to me it should have increased. I want to know what i might be missing or where i am getting wrong.
these are the variation in new models as compared to previous based on simulating it at trip point.
Pmos--> current has been increased by 20%,vt reduced by 11% and gate cap is reduced by 2% (approx numbers)
NMOS -->almost same

Regards

 

[timof]

"Faster" device means higher DC current.
Current through VDD is not DC (unless it's a DC leakage), but switching, transient.
The fact that it's lower is good (lower dissipated power).

Don't forget to simulate this using post-layout netlists, as parasitics may increase, and may dominate the circuit behavior.

 

[Sambhav_1]

"Faster" device means higher DC current.
Current through VDD is not DC (unless it's a DC leakage), but switching, transient.
The fact that it's lower is good (lower dissipated power).

Don't forget to simulate this using post-layout netlists, as parasitics may increase, and may dominate the circuit behavior.

So the only reason is less load?So if the sizes in new and old technologies were same then how can the current be decreased ?

 

[timof]

There are many things that may be different between old and new technology, even for the same device size: leakage current, drive current, load capacitance, VDD, etc.