Variable size and referenced array in SystemVerilog using `ifdef

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BartlebyScrivener

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I want to pipeline a design. There are a possible four pipeline stages, and I want to be able to control the number of pipeline stages compiled using a config file.

In the config file I want to have the following

Code:
`define PL1
`define PL2
`define PL3
`define PL4

so that I can use
Code:
`ifdef PL3
in my code to add the respective registers. I would like any combination of pipe line stages to be used or not used.

My question is, to control my pipeline, I want an array that will be used for clock enables. If all pipeline stages were defined, this would be a 4 bit array representing {PL1, PL2, PL3, PL4}. However, if say, only 2 pipeline stages were defined, PL2 and PL4, I would like a 2 bit array representing {PL2, PL4}.

Is there a neat way of creating this array?
 

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