Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Variable gain amplifier DC output voltage bias

Status
Not open for further replies.

AllenD

Member level 5
Joined
Aug 7, 2017
Messages
91
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
1,193
Hi team
I have some trouble with Variable gain amplifier(VGA) DC output voltage bias. The topology is shown the attached picture.
VGA.png

I understand that if Vb=Vdd, M3 is off, Vout_DC is decided by the gm1/gm2 amplifier. However, when Vb gets smaller, and M3 start to turn on and draw current, Vout_DC should be increased. The more current the M3 draw, the higher the Vout_DC is.

Won't this limit the output voltage range? I could not find any paper discuss this issue and it seems they don't think it's a problem. Hence I suspect I must miss something here...

Can anyone help, please.
Thanks
Allen
 

Obviously M3 have to operate in saturation, otherwise the gain will decrease with the increasing Ids3(Ix on the figure), and yes, headroom will decrease radically. The output range is limited by the diodes itself, and with an other stage you can get much higher heardroom, which has constant gain.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top