module Booth_Multiplier (
input Rst,
input Clk,
input Ld,
input [31:0] M,
input [31:0] R,
output reg Valid,
output reg [(64 - 1):0] P
);
reg [32:0] A;
reg [ 32:0] Cntr;
reg [32:0] S;
reg [(64 + 1):0] Prod,Prod2;
always @(*)
begin
case(Prod[1:0])
2'b01 : S = Prod[(64 + 1):(32 + 1)] + A;
2'b10 : S = Prod[(64 + 1):(32 + 1)] - A;
default : begin
S = Prod[(64 + 1):(32 + 1)];
end
endcase
end
always @(posedge Clk)
begin
if(Rst) begin
A <= #1 0;
skip <= #1 0;
Prod <= #1 0;
P <= #1 0;
Valid <= #1 0;
Cntr <= #1 0;
end
else if(Ld) begin
A <= #1 {M[31], M};
Prod <= #1 {R, 1'b0};
Cntr <= #1 32;
end
else if(Cntr > 1) begin
Cntr <= #1 (Cntr - 1);
Prod <= #1 {S[32], S, Prod[32:1]};
end
else if(Cntr == 1) begin
P <= #1 {S[32], S, Prod[32:2]};
Valid <= #1 (Cntr == 1);
end
end
endmodule