V BAND RF AMPLIFIER / INPUT MATCHING

[Faizan shafi]

I am designing a v band lna . I have done the dc biasing and the s parameter simulation.
I have shared the schematic below. The blue circle has my biasing network. the yellow arrows point to input nd output ports. red indicates the blocking capacitors.

I am following a tutorial , and i have shared a section of it below.

I have found my input impedance which is 9.690 -25.092j.

I am really confused about the forced matching part. Where should I connect this 50 ohm resistor? In my main schematic or when i open my Smith chart tool and plug in zs and zin and then in the middle of these two should I put my 50 oh resistor.

Will this blocking capacitor be a part of my matching network or will i simply remove it after making the matching network.

can someone please explain me the steps of how should i move forward. Thank you.

 

[BigBoss]

There is nothing to force Input Matching here.
If your intention to design an Low Noise Amplifier, all you have to do is to find Optimum Noise Impedance then match this Impedance to 50 Ohm.
That's it.
No additional options are considered here. 50 Ohm termination resistances are used for the circuits that have very high input impedance to prevent reflection for the waves coming from a long road. Here, your case is completely different.

 

[FvM]

Blocking capacitors C3 and C4 are necessary for circuit operation and can't be removed unless your final matching network is providing AC coupling as well. Capacitance of 1 uF is uselessly high for microwave amplifier, you'll rather use 100 pF or so. But as long as you are using ideal capacitor in your simulation circuit, the values isn't important.

 

[vfone]

Ignoring the fact that you use 1uF DC blocking capacitors at 75GHz (which is totally nonsense), I think that finding even 1pF discrete capacitors working at 75GHz, would be a problem.
Using the online SimSurfing from Murata, if choose the smallest SMD capacitor dimension they have (01005 - 0.22mm) the 1pF capacitor have the resonant frequency at 12.7GHz. From 12.7GHz up to 75GHz the 1pF is not a capacitor anymore, but is an inductor.

SimSurfing

SimSurfingは村田製作所の製品情報、生産情報、特性データ、シミュレーション、カタログ出力など、さまざまな情報を提供するオンラインソフトウェアです。

ds.murata.co.jp

 

[volker@muehlhaus]

I think that finding even 1pF discrete capacitors working at 75GHz, would be a problem.

The simulation schematic shows that this is an RFIC technology (IHP SG13G3 Cu). That technology offers MIM capacitors which work fine in the required frequency range for DC blocking.

I had developed capacitor models for that technology and have some data available: w=10um l=10um has C=213fF and measured insertion loss of less than -0.3dB between 40 GHz and 110 GHz.

 

[vfone]

If a 213fF works up to 110GHz, is no guarantee that a 1pF capacitor would work at 75GHz.
Looking to this process I see capacitors only in fF range..
1uF cap, even if it is outside of the chip, is a nonsense at 75GHz..

 

[volker@muehlhaus]

If a 213fF works up to 110GHz, is no guarantee that a 1pF capacitor would work at 75GHz.

True, self resonance depends on size, and larger C values are larger in size -> lower SRF.

That is why I recommended to use 10um x 10um MIM capacitor for this frequency range in this technology. The ADS library for SG13G3 Cu includes the MIM model.

 

[Faizan shafi]

Thank you all to your replies. They helped me in one way or another.
Now I moved little forward in my designing and I need your opinions about it.

First pictures shows me the results of my simulation without the matching network.
I read in a book that the general way for LNA matching is that you match on the input side for Minimum noise figure and on the output side for max gain.

If you look at the picture 1, It shows me the values for impedance matching.
That is what i did. I matched my 50 ohm source impedance to Zopt. which is 29.1+j*7.21 .
and on the output side I did the conjugate load matching , which is 50 ohm to 220.569 -j*47.323.

Picture 2 shows me the results after matching. I did achieve some goals. but

I have few confusions .
1- my S11 and S22 are bad . like really bad. And i don't know the reason for it.
2- I know that when i connected my input matching block and output matching block. They effected each other. I know its stupid question but how can i see how much impedences have been effected by each other. My intension was to bring 50 ohm to Zopt on input side and Zl(50 ohm) to conjugate Zout. How can i see that did i succeed in doing that or not? That's my biggest confusion right now.


Picture 3 is the results that changed as compared to picture 1 after connecting my matching results.

I am having trouble understanding or interpreting the results that I have got from attaching my input output matching blocks. Can someone please help me explain these results and the problems so that i know how to solve them. Thank you.

 

[hskw_ha]

Thank you all to your replies. They helped me in one way or another.
Now I moved little forward in my designing and I need your opinions about it.

First pictures shows me the results of my simulation without the matching network.
I read in a book that the general way for LNA matching is that you match on the input side for Minimum noise figure and on the output side for max gain.

If you look at the picture 1, It shows me the values for impedance matching.
That is what i did. I matched my 50 ohm source impedance to Zopt. which is 29.1+j*7.21 .
and on the output side I did the conjugate load matching , which is 50 ohm to 220.569 -j*47.323.

Picture 2 shows me the results after matching. I did achieve some goals. but

I have few confusions .
1- my S11 and S22 are bad . like really bad. And i don't know the reason for it.
2- I know that when i connected my input matching block and output matching block. They effected each other. I know its stupid question but how can i see how much impedences have been effected by each other. My intension was to bring 50 ohm to Zopt on input side and Zl(50 ohm) to conjugate Zout. How can i see that did i succeed in doing that or not? That's my biggest confusion right now.


Picture 3 is the results that changed as compared to picture 1 after connecting my matching results.

I am having trouble understanding or interpreting the results that I have got from attaching my input output matching blocks. Can someone please help me explain these results and the problems so that i know how to solve them. Thank you.

I guess you put the resistor too much.
Typically resistor makes loss.

some proper resistor makes transistor more stable but there;'s too many resistor in your bias schematic line.