UVM with VHDL or VHDL-AMS

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You can IIRC, but all the underlying code is System Verilog, so I think you'll need a licence that will allow you to run mixed mode. You need to create the component declaration in VHDL in your code to link it to the UVM module.

Here is a beginners guide:
**broken link removed**
 
yourcheers said:
you can directly instantiate VHDL module in verilog file in verilog syntax.
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Hi yourcheers,

My question is how to follow the UVM benefits, like the class concepts and the interface concepts bring to the VHDL environment ?
 

Probably not in any easy way you would like. You'd need some sort of standard way to go between the SV language constructs and VHDL. That would mean either you write some wrappers or you find some collection of macros/whatevers that do this work for you.

Now the problem of "use UVM with VHDL with maximum benefits" sounds general enough that people have already invested time in that. Googling on "vhdl uvm class" finds some useful stuff.
 

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