Usually we sample at rising edge and setup at falling edge of a clock?

[kaushikrvs]

Usually we sample at rising edge and setup at falling edge of a clock? but Verilog says not to use both clock edges in a module so which one has to be followed?

 

[KlausST]

Hi,

Both is true.

* you should not do this to synchronize input data with your high speed FPGA system clock
* but it's common for (relatively low speed) signals like the SPI interface...related to the SPI clock.

Klaus

 

[dpaul]

Normally people use the rising edge. You can use any one and use only that edge through the entire design.
But NEVER use both edges in the same design.

 

[vGoodtimes]

Sampling on a different edge is done for low speed interfaces between ICs. The goal is to make hold time easier to meet as the data/clock might have different length/loading.

Within a FPGA/ASIC, the hold times can be corrected during the build -- this makes a single clock-edge solution better. There is no duty-cycle issues and setup times are easier to meet and logic is easier to understand.

The 2 edge clocking is used mostly for external IO purposes as a result.

 

[ads-ee]

Usually we sample at rising edge and setup at falling edge of a clock? but Verilog says not to use both clock edges in a module so which one has to be followed?

Nowhere in the Verilog LRM says that you can't use both clock edges in a module....

What is not allowed is using a posedge and negedge clock in the same always block. It's true, it will simulate without a problem but it is absolutely not synthesizable code as there aren't any libraries (that I know of) that contain a both edges sensitive flip-flop.

I think you need to read a good book on Verilog or at least a decent book that distinguishes between non-synthesizable and synthesizable code.

 

[barry]

Normally people use the rising edge. You can use any one and use only that edge through the entire design.
But NEVER use both edges in the same design.

You mean like DDR designs?

 

[dick_freebird]

I've seen many standard cell libraries offering both
positive and negative edge clocked flip-flops. The
setup time and the hold time both pertain to the
active clock edge. If you have enough clock period
(and duty cycle consistency) to accommodate
these keepout times and any intermediate (logic
prop) delays there's no reason you can't clock on
both edges even inside a single logic block. But
the timing analysis is probably on you, and maybe
synthesis tools aren't supportive (I only do hand
wired logic, still, and only am called upon to do it
when synthesis based, standard cell library approach
can't make it).

 

[dpaul]

You mean like DDR designs?

I assumed the OP is talking about normal RTL logic design.
I intentionally didn't comment about DDR (there are flops in FPGA that can do that) and using both clk edges in the same design in different always block (if timing problems occur then it would be easier to analyze them when only 1 clk edge is used for the entire design) for simplicity.

 

[ads-ee]

I've seen many standard cell libraries offering both
positive and negative edge clocked flip-flops.

Not sure if this was directed at post #5, but I wasn't referring to positive edge and negative edge clocked flip-flops. I was specifically stating I've never seen any libraries with a positve-negative edge clocked flip-flop i.e. a flip-flop that changes it's output on both edges of a clock. DDR registers that I've seen seem to have both rising and falling edge flip-flops and a mux controlled by the clock to select the output.

 

[barry]

There is no rule about using both edges in a design. The timing engine will take this into account when routing the design. Basically, a design that uses both edges will just have to meet a timing constraint of twice the specified frequency. I think all modern tools are capable of resolving this type of design.

 

[ThisIsNotSam]

I've seen many standard cell libraries offering both
positive and negative edge clocked flip-flops. The
setup time and the hold time both pertain to the
active clock edge. If you have enough clock period
(and duty cycle consistency) to accommodate
these keepout times and any intermediate (logic
prop) delays there's no reason you can't clock on
both edges even inside a single logic block. But
the timing analysis is probably on you, and maybe
synthesis tools aren't supportive (I only do hand
wired logic, still, and only am called upon to do it
when synthesis based, standard cell library approach
can't make it).

modern ASIC tools can handle it transparently.