Use Design Compiler to synthesize the Verilog RTL into a Verilog gate-level netlist.
Then you can import the Verilog netlist into Synopsys Custom Designer, if you have it, and simulate through that.
If not, providing you have the transistor levels models for the standard cells, you should be able to simulate with that. You will just need to use a netlisting program to create a spice netlist from the gate-level Verilog. Something like v2lvs, nettran etc. Depends what other tools you have.