Using unconstained input ports in VHDL 2008

shaiko · Jun 23, 2014

Using VHDL 2008, I defined port "A" as an uncontrained "unsigned" input to my entity:

Code:

entity some_entity is
port	
( A : in unsigned ) ;   
end entity some_entity;

In my test bench, I declared signal "B" as follows:

Code:

signal B: unsigned ( 7 downto 0 ) ;

I connected signal "B" to port "A" and compiled the design.
Parsing check passes without issues. However, when I try to simulate - Modelsim (10.3b) shows an error:

Fatal: (vsim-3347) Port "A" is an unconstrained array.

i'm baffled. What's the issue?

TrickyDicky · Jun 23, 2014

Post the whole code

shaiko · Jun 23, 2014

the entity:

Code:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;

entity some_entity is
port ( A : in unsigned ) ;
end entity some_entity ;

architecture architecture_some_entity of some_entity is
begin
end architecture architecture_some_entity ;

The test bench:

Code:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;

entity tb_some_entity is
end entity tb_some_entity ;

architecture simulation_tb_some_entity of tb_some_entity is

component some_entity is
port ( A : in unsigned ) ;
end component some_entity ;

signal B : unsigned ( 7 downto 0 ) ;

begin

B <= ( others => '1' ) ;

connect : some_entity
port map
( A => B ) ;

end architecture simulation_tb_some_entity ;

K-J · Jun 23, 2014

The error is because you tried to simulate 'some_entity' rather than the testbench 'tb_some_entity'.

Kevin Jennings

shaiko · Jun 23, 2014

What do you mean?
"some_entity" is the entity and it's described in "some_entity.vhd".
This entity is being instantiated as a component and connected in the port map of "tb_some_entity.vhd"
Both files are compiled and added to the simulation as follows:

What should I do differently?
How should I rewrite it?

K-J · Jun 23, 2014

You don't have to rewrite any code. When you try to simulate the testbench 'tb_some_entity' there are no errors, Modelsim starts the simulation just fine.

What you actually did is tried to simulate the 'some_entity' component directly using the Modelsim command 'vsim some_entity'. When you do that you get the error that you reported because at elaboration time (i.e. trying to start the simulation), the size of port 'A' is not defined.

If you do want to simulate 'some_entity' standalone without even the testbench for some reason, then you need to define the width of A with a generic like this...

Code:

entity some_entity is
generic( A_width: natural);
port ( A : in unsigned(A_width-1 downto 0) ) ;
end entity some_entity ;

Then when you go to start a simulation of 'some_entity' by itself, you would specify the value of the generic 'A_width' as part of the vsim command line. One downside to using unconstrained vectors on ports is that you cannot simulate them directly. However, since the usual mode of simulating is to use a testbench, that downside goes away because the testbench connection to the component through the port map will define the entity's unconstrained port.

Kevin Jennings

Using unconstained input ports in VHDL 2008

shaiko

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TrickyDicky

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shaiko

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K-J

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K-J

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