Using the clock gating technique

Hi all,
I'm using a simple divide by 2 Frequency divider circuit designed with an asyncronous reset flip-flop to get 50 Mhz from a reference clock of 100 Mhz. The resulting low speed clock s used to synchronise another circuits. I use the reset pin of the Frequency divider to enable and disable the synthesis of the low speed clock.

Is that technique a Clock gating technique ?

Clock gating ?

If the clock only goes through an AND gate - then yes. If it goes through the D and out of the Q pins of a FF then no.

Re: Clock gating ?

Please look at the circuit below,

When the Control signal is low, the circuit divide the input frequency and generate a 50 Mhz Clock Signal, when the Control signal is high the output is zero.

Is that a clock gating ?

Clock gating ?

you divided the clock, not gated it.
you can think of gated clock as transferring edges or not.
if you would want to have half the frequency by clock gating, the duty cycle of your out clock would change from the 50% you have now.

ND
https://asicdigitaldesign.wordpress.com

Re: Clock gating ?

No, the circuit shows a divider, not clock gating.

Clock gating is a low-power technique whereby you switch off certain branches of the clock tree when that part of the logic is not needed. This saves a lot of power by preventing needles switching of those FFs and clock buffers.

A clock gate in its simplest form is an AND gate with pin A connected to the clock and pin B connected to an 'enable' signal. If the enable is high then the clock passes through the AND. If the enable is low then the clock signal is blocked.

In practice, a clock gate needs a transparent latch as well. Most semiconductor libraries include several Integrated Clock Gating (ICG) cells that implement a complete clock gate circuit with a latch, test enable, regular enable and clock input/outputs.[/img]

Re: Clock gating ?

To Nir Dahan and Marcs,

I know perfectly that it is a frequency divider. My question is quite simple: As I explained, with the control signal we can command the frequency divider so that clock is generated when this signal is low and the clock is stoped when it is high.

Approximatively, the circuit is equivalent to the following circuit in which the 50 Mhz signal is ANDed with the Control signal ( A basic clock gating technique).

If you compare the 2 circuit they have the same function but not the number of gates count.
My goal is to reduce the area of my circuit.

I come back to the question : Can I call the technique in the first circuits as a gating ?

Thanks.

Re: Clock gating ?

Yes, logically it is equivalent to clock gating. There are however 2 points you need to check before you decide it works:

1. Where does the control signal come from? Is it generated from flops driven by the 50MHz clock you are switching off? Are you sure the control timing is fast enough to block the correct clock edge? What about extra transitions caused by race conditions on the reset? You will also have to guarantee that there is never a glitch on the reset signal. I don't know the behavior of your gate or the source of your control signal, but I get a bad feeling about the practical reliability of this "clock gate".

2 If your goal is to save area you may also want to investigate whether a resetable flip-flop is really smaller than a regular flop plus a normal clock gate.

Re: Clock gating ?

MarcS said:

Yes, logically it is equivalent to clock gating. There are however 2 points you need to check before you decide it works:

1. Where does the control signal come from? Is it generated from flops driven by the 50MHz clock you are switching off? Are you sure the control timing is fast enough to block the correct clock edge? What about
2 If your goal is to save area you may also want to investigate whether a resetable flip-flop is really smaller than a regular flop plus a normal clock gate.

Click to expand...

Thanks Marcs for the valuable informations.
The control signal comes from dff driven by 50 Mhz. The circuit runs perfectly. But I couldnt classify it as a gating techniques that's why I need the opinion of friends in this forum. Maybe somebody used it before and know the advantages and the drawback of a such technique.

Btw, I wanna know more what do you mean by:

extra transitions caused by race conditions on the reset?
glitch on the reset signal.

Click to expand...

Could you please tell me why

but I get a bad feeling about the practical reliability of this "clock gate".

Click to expand...

What tests and verifications have I to do in order to be sure that the circuit is reliable ?

Concerning your second point, a dff with reset can be obtained after introducing a simple modification to a simple dff (using 1 nmos and 1 pmos)
And gate is composed of 6 Transistor

The circuits 1 uses less transistors than the second one. At the end I will gain 4 transistor (so less area and consumed power).

Re: Clock gating ?

Hi Mouzid:

The big problem with clock gates that you absolutely have to verify is that in the logical space the clock signal is "ideal". This means that it magiacally shows up at all the clock pins at the same time.

In a real circuit, you have to synthesize a clock tree to distribute this clock signal and this involves real delays. This is called "propagated mode". Because the ideal mode STA doesn't know what the clock insertion delay is to each flip-flop, it is impossible for it to really know if the enable timing will work or not.

For example: You say the control signal comes from the FFs driven by the 50MHz signal. What if the delay from your 50Mhz clock source pin to the FFs is 23ns? Will your circuit still work? Check setup and hold times to make sure.

So you need to specify target insertion delays and target skews in the SDC that match what you think is feasible, and then re-simulate. Find out how much insertion delay you can tolerate before it stops working.