Using system verilog DDR4 simulation models in VHDL.

// MICRON TECHNOLOGY, INC. - CONFIDENTIAL AND PROPRIETARY INFORMATION
interface DDR4_if #(parameter CONFIGURED_DQ_BITS = 8) ();
    timeunit 1ps;
    timeprecision 1ps;
    import arch_package::*;
    parameter CONFIGURED_DQS_BITS = (16 == CONFIGURED_DQ_BITS) ? 2 : 1;
    parameter CONFIGURED_DM_BITS = (16 == CONFIGURED_DQ_BITS) ? 2 : 1;
    logic[1:0] CK; // CK[0]==CK_c CK[1]==CK_t
    logic ACT_n;
    logic RAS_n_A16;
    logic CAS_n_A15;
    logic WE_n_A14;
    logic ALERT_n;
    logic PARITY;
    logic RESET_n;
    logic TEN;
    logic CS_n;
    logic CKE;
    logic ODT;
    logic[MAX_RANK_BITS-1:0] C;
    logic[MAX_BANK_GROUP_BITS-1:0] BG;
    logic[MAX_BANK_BITS-1:0] BA;
    logic[13:0] ADDR;
    logic ADDR_17;
    wire[CONFIGURED_DM_BITS-1:0] DM_n;
    wire[CONFIGURED_DQ_BITS-1:0] DQ;
    wire[CONFIGURED_DQS_BITS-1:0] DQS_t;
    wire[CONFIGURED_DQS_BITS-1:0] DQS_c;
    logic ZQ;
    logic PWR;
    logic VREF_CA;
    logic VREF_DQ;
endinterface

  component DDR4_if
  generic(
    CONFIGURED_DQ_BITS  : natural
  );
  port(
    CK        : in    std_logic_vector(1 downto 0);
    ACT_n     : in    std_logic;
    RAS_n_A16 : in    std_logic;
    CAS_n_A15 : in    std_logic;
    WE_n_A14  : in    std_logic;
    ALERT_n   : out   std_logic;
    PARITY    : in    std_logic;
    RESET_n   : in    std_logic;
    TEN       : in    std_logic;
    CS_n      : in    std_logic;
    CKE       : in    std_logic;
    ODT       : in    std_logic;
    C         : in    std_logic_vector(2 downto 0);
    BG        : in    std_logic_vector(1 downto 0);
    BA        : in    std_logic_vector(1 downto 0);
    ADDR      : in    std_logic_vector(13 downto 0);
    ADDR_17   : in    std_logic;
    DM_n      : in    std_logic_vector(0 downto 0);
    DQ        : inout std_logic_vector(7 downto 0);
    DQS_t     : inout std_logic_vector(0 downto 0);
    DQS_c     : inout std_logic_vector(0 downto 0);
    ZQ        : in    std_logic;
    PWR       : in    std_logic;
    VREF_CA   : in    std_logic;
    VREF_DQ   : in    std_logic
  );  
  end component DDR4_if;