Using system verilog DDR4 simulation models in VHDL.

[franskennis]

I have downloaded a system verilog DDR4 simulation model from Micron and want to use that in my VHDL testbench.

The interface of the system verilog DDR4 memory model from Micron:

// MICRON TECHNOLOGY, INC. - CONFIDENTIAL AND PROPRIETARY INFORMATION
interface DDR4_if #(parameter CONFIGURED_DQ_BITS = 8) ();
    timeunit 1ps;
    timeprecision 1ps;
    import arch_package::*;
    parameter CONFIGURED_DQS_BITS = (16 == CONFIGURED_DQ_BITS) ? 2 : 1;
    parameter CONFIGURED_DM_BITS = (16 == CONFIGURED_DQ_BITS) ? 2 : 1;
    logic[1:0] CK; // CK[0]==CK_c CK[1]==CK_t
    logic ACT_n;
    logic RAS_n_A16;
    logic CAS_n_A15;
    logic WE_n_A14;
    logic ALERT_n;
    logic PARITY;
    logic RESET_n;
    logic TEN;
    logic CS_n;
    logic CKE;
    logic ODT;
    logic[MAX_RANK_BITS-1:0] C;
    logic[MAX_BANK_GROUP_BITS-1:0] BG;
    logic[MAX_BANK_BITS-1:0] BA;
    logic[13:0] ADDR;
    logic ADDR_17;
    wire[CONFIGURED_DM_BITS-1:0] DM_n;
    wire[CONFIGURED_DQ_BITS-1:0] DQ;
    wire[CONFIGURED_DQS_BITS-1:0] DQS_t;
    wire[CONFIGURED_DQS_BITS-1:0] DQS_c;
    logic ZQ;
    logic PWR;
    logic VREF_CA;
    logic VREF_DQ;
endinterface

The VHDL component declaration:

  component DDR4_if
  generic(
    CONFIGURED_DQ_BITS  : natural
  );
  port(
    CK        : in    std_logic_vector(1 downto 0);
    ACT_n     : in    std_logic;
    RAS_n_A16 : in    std_logic;
    CAS_n_A15 : in    std_logic;
    WE_n_A14  : in    std_logic;
    ALERT_n   : out   std_logic;
    PARITY    : in    std_logic;
    RESET_n   : in    std_logic;
    TEN       : in    std_logic;
    CS_n      : in    std_logic;
    CKE       : in    std_logic;
    ODT       : in    std_logic;
    C         : in    std_logic_vector(2 downto 0);
    BG        : in    std_logic_vector(1 downto 0);
    BA        : in    std_logic_vector(1 downto 0);
    ADDR      : in    std_logic_vector(13 downto 0);
    ADDR_17   : in    std_logic;
    DM_n      : in    std_logic_vector(0 downto 0);
    DQ        : inout std_logic_vector(7 downto 0);
    DQS_t     : inout std_logic_vector(0 downto 0);
    DQS_c     : inout std_logic_vector(0 downto 0);
    ZQ        : in    std_logic;
    PWR       : in    std_logic;
    VREF_CA   : in    std_logic;
    VREF_DQ   : in    std_logic
  );  
  end component DDR4_if;

When I instantiate this module in my testbench I got the following error in Modelsim:

# Loading work.DDR4_if
# ** Error: (vsim-3062) Cannot instantiate a module with unnamed ports from VHDL.
# Time: 0 ns Iteration: 0 Instance: /ddr_sim_model_wrapper/DDR4_mem_model_i File: c:/Projects/ddr4_example_design/simulation/ddr4_sim_model/interface.sv
# Error loading design

Does someone know what I doing wrong?

 

[TrickyDicky]

Oh Good, a SV model with Verilog 1995 style ports.
The awkwardness is probably the parameters. Your port sizes dont match for when CONFIGURED_DQ_BITS=16 (because some ports use the CONFIGURED_DQS_BITS and CONFIGURED_DM_BITS which are 2 or 1 depending on CONFIGURED_DQ_BITS generic.

 

[dave_59]

No, it a SystemVerilog interface with no ports. VHDL-2008 does not support interfaces - you have to manually connect each internal interface signal to the VHDL instance ports.

 

[TrickyDicky]

No, it a SystemVerilog interface with no ports. VHDL-2008 does not support interfaces - you have to manually connect each internal interface signal to the VHDL instance ports.

Thanks Dave - I didnt see the interface declaration - just assumed a module

 

[franskennis]

Thank you for the replies. Unfortunately I have only the interface DDR4_if, all other micron files are encrypted. How can i connect each internal interface signal to the VHDL instance ports?

Sorry but I'am not familiar with (System) Verilog.

 

[TrickyDicky]

The easiest way might be just to create a wrapper module thats connects all the interface signals to module ports. Then you can instantiate the module in the VHDL