Hi,everyone:
Could you give me a hand to solve following questions?
(1)I download the predictive technology model for 32nm finfet(double-gate) technologies from the website (
http://ptm.asu.edu) ,but I found one of the files , 32nm_finfet.pm, which described the double-gate used two parallel connection transistors, like this:
Is it true? Because I think the double-gate finfet isn't just parallel two transistors.
(2)I also download the 16nm finfet model(PTM-MG) and the 16nm cmos model(PTM LP model) ,and then measuring the leakage power and total power. I found the total power of 16nm cmos is far less than the total power of finfet ,is it true? And I measured the leakage power of cmos is similar to the leakage power of finfet. This is my spice file. By the way, I browsed this website(
https://www.edaboard.com/threads/202213/), but I don’t know whether I need to download bsim cmg model files? I do download this file, but I don’t know how to operate it. Now I use include .pm file to run the hspice model.
View attachment spice.7z
(3) how could I exactly measure the leakage power of hspice? As so far, I enter the input to keep it stable and look the power figure. Plazzzzzzz give me a hand to solve my problems. Finally, thank you for your reading.