gongdori
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Hello,
I just started studying PSL assertion for design verificaion. I am debugging a module which has programmable delay and it seems embeddeding PSL in VHDL code can be beneficial.
I want to describe a property of the data path of the module I am working on; I have two std_logic_vector signals as input and the output can be computed from the input and it should be available n number of clock cycles later.
Can you give me a pointer to solve this problem? If it is not possible to describe this property in PSL, can SVA describe it?
gongdori
I just started studying PSL assertion for design verificaion. I am debugging a module which has programmable delay and it seems embeddeding PSL in VHDL code can be beneficial.
I want to describe a property of the data path of the module I am working on; I have two std_logic_vector signals as input and the output can be computed from the input and it should be available n number of clock cycles later.
Can you give me a pointer to solve this problem? If it is not possible to describe this property in PSL, can SVA describe it?
gongdori