Using PHY MII in verilog!

Hi All!

I am trying Ethernet MAC PHY MII on spartan3e1600e development kit.
I have made a very simple receiver logic in verilog which simply works on rx_clk (2.5 MHz in my case since i am working on 10mbps) and rx_dv signal to display the received data nibble by nibble on the output.

The problem is that i am not getting any recognizable nibbles at output since it should be like
"06 05 04 03 02 01 FF FF FF FF FF FF 08 00 45 00 00 58 00 00 00 00 80 11 EA 6A 0A 14 1E 01 0A 14 1E 02 1F 90 1F 90 00 44 89 89 12 34 56 78 90 12 34 56 78 90 12 34 56 78 90 12 34 56 78 90 12 34 56 78 90 12 34 56 78 90 12 34 56 78 90 12 34 56 78 90 12 34 56 78 90 12 34 56 78 90 11 22 33 44 55 66 77 88 99 00 00"

ideally but i am getting some irregular data as monitored on FPGA KIt's IO pins... via Logic analyzer.

Can anybody tell me what could be the problem. whether i have to configure that some how?
Thanks in advance
Regards!

What are you getting on the output instead?

Expected Output:
"55 55 55 55 55 55 55 5D 06 05 04 03 02 01 FF FF FF FF FF FF 08 00 45 00 00 36 00 00 00 00 80 11 B9 4A C0 A8 00 08 C0 A8 00 14 1F 90 1F 90 00 22 4C 3E 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 20 20 21 22 23 24 25 00 00"

While what I am getting these nibbles for the presented data:
"AB 07 96 A9 4E 3F 63 07 96 A9 4E 0F 71 10 00 A2 00 00 6C 00 00 00 00 00 18 89 D5 20 31 50 01 00 31 50 02 8F 80 9F 80 90 04 43 27 C8 04 0C 02 0A 06 0E 01 09 00 88 84 8C 82 8A 86 8E 81 80 40 48 44 43 4C 42 4A 40 51 73 C8 E7 F8 00"