Using oscilator as a clock

[icd]

Hi,

I am trying to use a fast and slow clock oscillators as a two clocks to two 8-bit counters. The problem the 2 counters are not counting. They give me X as an output. I will appreciate any help to figure out the problem. below is my code and an image of the output:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

LIBRARY work;

ENTITY ring IS 
	PORT
	(
		en_slow :  IN  STD_LOGIC;
		en_fast :  IN  STD_LOGIC;
		slow_clk :  OUT  STD_LOGIC;
		fast_clk :  OUT  STD_LOGIC;
		counter1, counter2 : out std_logic_vector(7 downto 0)
	);
END ring;

ARCHITECTURE beh OF ring IS 

SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;

signal cnt1, cnt2 : std_logic_vector(7 downto 0):=(others=>'0');


BEGIN 
slow_clk <= SYNTHESIZED_WIRE_7;
fast_clk <= SYNTHESIZED_WIRE_2;



SYNTHESIZED_WIRE_1 <= NOT(SYNTHESIZED_WIRE_0);



SYNTHESIZED_WIRE_3 <= NOT(SYNTHESIZED_WIRE_1);



SYNTHESIZED_WIRE_8 <= en_fast AND SYNTHESIZED_WIRE_2;


SYNTHESIZED_WIRE_4 <= NOT(SYNTHESIZED_WIRE_3);



SYNTHESIZED_WIRE_5 <= NOT(SYNTHESIZED_WIRE_4);



SYNTHESIZED_WIRE_7 <= NOT(SYNTHESIZED_WIRE_5);



SYNTHESIZED_WIRE_9 <= NOT(SYNTHESIZED_WIRE_6);



SYNTHESIZED_WIRE_0 <= en_slow AND SYNTHESIZED_WIRE_7;


SYNTHESIZED_WIRE_6 <= NOT(SYNTHESIZED_WIRE_8);



SYNTHESIZED_WIRE_2 <= NOT(SYNTHESIZED_WIRE_9);


slow_clk_counter1_process : process(SYNTHESIZED_WIRE_7)
                  begin
                  if(SYNTHESIZED_WIRE_7'event and SYNTHESIZED_WIRE_7='1')then
                  cnt1<=cnt1+1;
                  end if;
                  counter1<=cnt1;
                  end process;

fast_clk_counter2_process : process(SYNTHESIZED_WIRE_2)
                  begin
                  if(SYNTHESIZED_WIRE_2'event and SYNTHESIZED_WIRE_2='1')then
                  cnt2<=cnt2+1;
                  end if;
                  counter2<=cnt2;
                  end process;



END beh;

 

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The code you posted doesn't even produce the waveforms shown.



- - - Updated - - -

oops my mistake I didn't set en_fast to low to start, still Modelsim hits a iteration limit as the "ring" keeps cycling in delta time and won't let the simulator reach a stable state. This code is probably not synthesizable. Why would you want to do this, what is the point?

- - - Updated - - -

adding delays to all the assignments....

SYNTHESIZED_WIRE_1 <= NOT(SYNTHESIZED_WIRE_0) after 10 ns;

results in the counters counting correctly.

 

[icd]

Thank u for ur help. I am using Quartus 9.1, so I show the WF without using modelsim and I did add delay but still not working. Is this what u meant by adding delay

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

LIBRARY work;

ENTITY ring IS 
	PORT
	(rst : in std_logic;
		en_slow :  IN  STD_LOGIC;
		en_fast :  IN  STD_LOGIC;
		slow_clk :  OUT  STD_LOGIC;
		fast_clk :  OUT  STD_LOGIC;
		counter1, counter2 : out std_logic_vector(7 downto 0)
	);
END ring;

ARCHITECTURE beh OF ring IS 

SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;

signal cnt1, cnt2 : std_logic_vector(7 downto 0):=(others=>'0');


BEGIN 
slow_clk <= SYNTHESIZED_WIRE_7 ;
fast_clk <= SYNTHESIZED_WIRE_2 ;



SYNTHESIZED_WIRE_1 <= NOT(SYNTHESIZED_WIRE_0) after 10 ns;



SYNTHESIZED_WIRE_3 <= NOT(SYNTHESIZED_WIRE_1) after 10 ns;



SYNTHESIZED_WIRE_8 <= en_fast AND SYNTHESIZED_WIRE_2 after 10 ns;


SYNTHESIZED_WIRE_4 <= NOT(SYNTHESIZED_WIRE_3) after 10 ns;



SYNTHESIZED_WIRE_5 <= NOT(SYNTHESIZED_WIRE_4) after 10 ns;



SYNTHESIZED_WIRE_7 <= NOT(SYNTHESIZED_WIRE_5) after 10 ns;



SYNTHESIZED_WIRE_9 <= NOT(SYNTHESIZED_WIRE_6) after 10 ns;



SYNTHESIZED_WIRE_0 <= en_slow AND SYNTHESIZED_WIRE_7 after 10 ns;


SYNTHESIZED_WIRE_6 <= NOT(SYNTHESIZED_WIRE_8) after 10 ns;



SYNTHESIZED_WIRE_2 <= NOT(SYNTHESIZED_WIRE_9) after 10 ns;


slow_clk_counter1_process : process(SYNTHESIZED_WIRE_7)
                  begin
                  if(rst='1')then
                  cnt1<=(others=>'0');
                  elsif(SYNTHESIZED_WIRE_7'event and SYNTHESIZED_WIRE_7='1')then
                  cnt1<=cnt1+1;
                  end if;
                  counter1<=cnt1;
                  end process;

fast_clk_counter2_process : process(SYNTHESIZED_WIRE_2)
                  begin
                  if(rst='1')then
                  cnt2<=(others=>'0');
                  elsif(SYNTHESIZED_WIRE_2'event and SYNTHESIZED_WIRE_2='1')then
                  cnt2<=cnt2+1;
                  end if;
                  counter2<=cnt2;
                  end process;



END beh;

when I used xilinx here is what I got


Is there any synthesizable code for ring oscillator I can get one slow clock and another one fast. That will help a lot.