spman
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Hi,
I have a board with two SFP+ ports. These ports are connected to MGTs in the same bank of FPGA. When I use one port, everything is ok.
For utilizing two ports simultaneously, I instantiated two PCS/PMA cores in the design and pass MGTREFCLK to both of them. But I got this error:
So I removed IBUFDS_GTE2 in both of the cores and instantiated one IBUFDS_GTE2 in the top module. But now there is another error:
I think the problem is because of using MGTs of same bank in different cores.
Could anyone please help me?
The FPGA is a Virtex-7
Thanks in advance.
I have a board with two SFP+ ports. These ports are connected to MGTs in the same bank of FPGA. When I use one port, everything is ok.
For utilizing two ports simultaneously, I instantiated two PCS/PMA cores in the design and pass MGTREFCLK to both of them. But I got this error:
Code:
ERROR:Place:1073 - Placer was unable to create RPM[BUFDS_RPMs] for the component
PHY_1/ten_gig_eth_pcs_pma_block/gt_usrclk_source/grefclk_ibufds_i of type
BUFDS for the following reason.
The reason for this issue:
The structured logic has to be merged with another RPM which causes a
placement violation for component
PHY_0/ten_gig_eth_pcs_pma_block/gt_usrclk_source/grefclk_ibufds_i. The
following components are part of this structure:
BUFDS PHY_1/ten_gig_eth_pcs_pma_block/gt_usrclk_source/grefclk_ibufds_i
IPAD SFP_CLK_MGT_NSo I removed IBUFDS_GTE2 in both of the cores and instantiated one IBUFDS_GTE2 in the top module. But now there is another error:
Code:
ERROR:Place:1390 - Unroutable Placement! A GTXE_COMMON / GT clock component pair
have been found that are not placed at a routable site pair. The GTXE_COMMON
component
<PHY_0/ten_gig_eth_pcs_pma_block/gtwizard_gth_10gbaser_i/gthe2_common_0_i> is
placed at site <GTHE2_COMMON_X1Y7>. The corresponding GT component
<PHY_0/ten_gig_eth_pcs_pma_block/gtwizard_gth_10gbaser_i/gt0_gtwizard_gth_10g
baser_i/gthe2_i> is placed at site <GTHE2_CHANNEL_X1Y27>. The pair can use
the fast path between them if the GTXE_COMMON and GT are both placed in the
same clock region. You may want to analyze why this problem exists and
correct it. This placement is UNROUTABLE in PAR and therefore, this error
condition should be fixed in your design. You may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING in order to generate an NCD file. This NCD file can then be used in
FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
clock placement rule is listed below. These examples can be used directly in
the .ucf file to demote this ERROR to a WARNING.
< PIN
"PHY_0/ten_gig_eth_pcs_pma_block/gtwizard_gth_10gbaser_i/gthe2_common_0_i.QPL
LOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN
"PHY_0/ten_gig_eth_pcs_pma_block/gtwizard_gth_10gbaser_i/gt0_gtwizard_gth_10g
baser_i/gthe2_i.QPLLCLK" CLOCK_DEDICATED_ROUTE = FALSE; >I think the problem is because of using MGTs of same bank in different cores.
Could anyone please help me?
The FPGA is a Virtex-7
Thanks in advance.