Using MOSFET as a switch

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polmin

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Hello, I'm new to the analog design world and I have some dumb questions about using a transistor as a switch in the circuit below.

for the NMOS, the transistor will act as a closed circuit if the gate-to-source voltage is higher than its threshold voltage. When it is the case, it will "pass" the source voltage to its output and we will be having -1V at the output of the circuit. But since the transistor won't be acting a perfect switch, there must be a voltage drop accros the mosfet which will lower the value of our output right? How is it possible to quantify this voltage drop?

And in terms of current, what current will be crossing the transistor?


Thank you.
 

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Hi,

As you wrote: To make the NMOS conductive V_gs needs to be higher than the V_gs_th.
It needs to be a couple if volts higher. The datasheet tells you details.

The voltage drop V_DS depends on the current. If the High side FET is OFF, then there is about zero current, thus about zero voltage drop.
When there is current at the output, then this will determine the voltage drop ... according Ohm's law using R_ds_on.

Your headline talks about "switch" which means "digital" operation. Either ON or OFF.
But in the text you talk about "analog" design. Not "switching".


Klaus
 

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The voltage drop on a MOSFET is Vds=Rdson*I, where Rdson is a MOSFET resistance in ON state, and I is the current.
It determines the power dissipation P=Vds^2/Rdson, and power efficiency of a DC-DC converter (static power dissipation part).

In power FETs, typical Rdson resistance is in 1-100 mOhm range.
Typical currents (in DC-DC converters) is from fraction of amp to several amps.

In an inverter, one of the MOSFETs is closed, so the current is zero, and voltage drop on the open MOSFET is zero too - so that output voltage is equal to Vss or Vdd voltage.
 

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You just contradicted yourself. If there is a I*Rds voltage drop, then the output voltage can’t possibly be Vdd or Vss.

Further, the voltage across the open FET is not zero, it’s Vdd(or Vss) minus the output voltage.
 

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barry said:
You just contradicted yourself. If there is a I*Rds voltage drop, then the output voltage can’t possibly be Vdd or Vss.

Further, the voltage across the open FET is not zero, it’s Vdd(or Vss) minus the output voltage.
Click to expand...

There is no contradiction.
If current is zero (like in an inverter, in steady state), the voltage drop on MOSFET is zero, and output voltage is Vss or Vdd.

In DC-DC converter, the current, going to the output (inductor and capacitor), is not zero, and voltage drop Vdd on a MOSFET is not zero.
 

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On resistance is selected /designed against the source & load attributes and accuracy required. For example a 1 ohm Ron and a 1Mohm Zin at the far side is a 1E-6 gain error, not bad, but 100 ohms and you're starting to touch 16b ADC's delivered accuracy; 100nA pin leakage into that 1M puts you below 7b in a 10V full scale system.

This is why so many permutations of "simple" switch piece parts, offering different balances of leakage and series resistance, through- and shunt-C for different lineup care-abouts
 

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