Using high impedance state with Verilog register

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SamV

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Hi All,

Today I thought I was clever by using a high impedance state in verilog. It doesn't work when I simulate it. Below is effectively what I was trying to do. Based on the simulation it seems that the if statement in the second always block which should check if the register set has a value of 1'bz doesn't work even though the value in the register is 1'bz. Is this what I should expect? If so, is there a way of doing this?

Thanks,
Sam
Code Verilog - [expand]
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always @(a or b or c)
 
begin
 
if(a|b|c)begin
if(a == 1'b1) 
set <= 1'b1;
else if (b == 1'b1)
set <= 1'b0;
else if (c == 1'b1)
set <= 1'bz;
end
 
end
 
 
 
always @(posedge clk)
 
begin
 
if(set == 1'b1)
x <= 1'b1;
else if(set == 1'b0)
y <= 1'b1;
else if(set == 1'bz) 
q <= 1'b1;
end
 
Last edited by a moderator:

From the LRM IEEE Std 1800-2012 11.4.5 Equality operators:


which means the result is always false as the compare fails.

The equality operator you want to use is === or !===:



More importantly this type of code is NOT synthesizable, if this is used only in a testbench that's okay as you may actually need to check for a Z value on some pin.
 
The only part of FPGA that may go to high impedance are I/O pins.

Same thing happen with 'u', 'x'. FPGA cannot set any internal component to 'x','z' or 'u', only to '0' and '1'.

Read the datasheet/user manuals of the FPGA you are using, there is a lot of interesting information there.
 
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    SamV

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Thank you for your reply! This is basically what I thought I would here. I've worked with High impedance states for i2c ...
 


Are you sure? I think it's synthesizable for sure. I've actually never seen the {3{=}} operator before in any of the online references. I'm using verilog 2001 I believe. I've read people talking about how the initial keyword is not synthesizable before but it definitely is is many Xilinx FPGA's

- - - Updated - - -


Oh, I see what you are saying I think. Correct me if I'm wrong please. The case equality operator === is used for comparisons when using values other than 0 and 1, like x or z. The case equality operator === is not synthesizable. Thanks!
 

You can't physically make hardware (synthesis) that can compare for X, that means both 0 or 1 are okay, basically the hardware generated is don't care so ends up being removed.

I really dislike comparisons done using don't care values. If you have a don't care condition e.g. address decoding.
Code Verilog - [expand]
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// using a don't care condition on the address bits
assign decoded_addr = (ADDR === 16'b0001_0000_000X_XXXX) ? 1'b1 : 1'b0;
 
// I think its better to explicitly define the address range you are using.
assign decoded_addr = (ADDR[15:5] == 11'h080) ? 1'b1 : 1'b0;


I also think long binary assignments are unreadable.
 

ads-ee said: 
Code Verilog - [expand]
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// using a don't care condition on the address bits
assign decoded_addr = (ADDR === 16'b0001_0000_000X_XXXX) ? 1'b1 : 1'b0;
Click to expand...

I don't know Verilog well enough to say if the code above is OK for synthesis, but direct compare with 'X' (unknown) or '-' (don't care) is not ok for synthesis in VHDL.
In VHDL, only an 'X' will match an 'X' and a '-' will only match a '-' in a normal compare, so it is only useful in a test bench.
To use "don't care" in a synthesizeable compare, you should use the "std_match" function (which also is my nickname on Edaboard!).
This is the VHDL code that corresponds to the intention of the Verilog code above:
Code VHDL - [expand]
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decoded_addr <= std_match(ADDR, "00010000000-----");
 

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