Using Functional data pin as Shift Enable signal

[ashwinvl]

Hi, I am using Encounter RTL Compiler to insert scan chains (muxed-scan) in my design..
I do not have a dedicated shift enable port and hence I am using a functional data pin as my shift-enable signal in the test mode..

But I come to know that I need to insert a test point manually, at this functional pin fanout inorder to gate the shift enable logic path (i.e prevent logic values at this port to travel thro' shift enable path in functional mode). I understand the purpose but am unable to zero-in on a test-point instance,i.e what logic should be inserted??... Will a 2-i/p AND gate on the shift-enable logic path with one input connected to a test control signal be sufficient??

Someone kindly help.. Thank u

 

[kornukhin]

If test mode and work mode will not use simultaneously you can add simple AND gate. I made so.

 

[ashwinvl]

Thanx a lot..
I have a doubt here.. The AND gate works fine when in FUNCTIONAL MODE.
But when in TEST MODE the shift-enable should be '1' for shift ('0' for capture cycle)... Wont this affect the logic path (for which this pin is an input) which has to be tested? I mean you have no control or controllability on this data pin for test generation..

 

[rca]

we currently used the following command in RC to indicate to used the internal signal "scan_shift", in sub_module test, as shift_enable.

"define_dft shift_enable -name shift_ncapture -active high -hookup_pin {i_test/scan_shift} pin_A"

The rtl code inside test module only made the following connection:

entity test is
port(
scan_mode : IN std_logic;
pin_A : IN std_logic;
shift_enable : OUT std_logic
);

architecture A of test is
begin
scan_shift <= pin_A when scan_mode='1' ELSE '0';
end;

To avoid the tool to remove this signal "unused" in the functionnal logic, you must add the next command after elaboration and before any synthesis:
"set_attribute prune_unused_logic false {i_test/scan_shift}"

---------- Post added at 10:04 ---------- Previous post was at 10:03 ----------

and that's work pretty well.

same idea for all scan mode....

 

[ashwinvl]

Thank u rca..
I think this logic is similar to the insertion of AND gate.. where 'pin_A' can be thought of functional pin(one i/p of AND gate), 'scan_shift' is the o/p of AND gate with 'scan_mode' as control i/p to the AND gate.. or can be thought of as a MUX too..This works absolutely fine in functional mode.

Anyway, my question is when in test mode, doesnt this affect the test generation,i.e in this case 'pin_A' has to be '1' throughout during shift,but at the same time it is also a functional data pin which is an i/p to a combinational logic to be tested.. So doesn't this hamper test generation.. I hope u got my point..
Kindly correct me if I am wrong..

 

[Fahmy]

I think you may need to add a test point at this point to enable the controllability of this point . There must be some way to do that automatically, I don't know how exactly.
Anyway, if you want to add it manually in the RTL code then you need to add a dummy flop and a mux controlled by the test_mode pin . in test mode the mux selects the output of the dummy flop and discards the external pin (shift enable) , while in functional mode the mux selects the external input .

 

[ashwinvl]

I think you may need to add a test point at this point to enable the controllability of this point . There must be some way to do that automatically, I don't know how exactly.
Anyway, if you want to add it manually in the RTL code then you need to add a dummy flop and a mux controlled by the test_mode pin . in test mode the mux selects the output of the dummy flop and discards the external pin (shift enable) , while in functional mode the mux selects the external input .

Going by your explaination, can you tell me..
1) what is the input to the dummy flop? and
2) to which point are you connecting the shift-enable net
I assume the output of the mux is going to the logic path (which should be in this case).

 

[Fahmy]

Going by your explaination, can you tell me..
1) what is the input to the dummy flop? and
2) to which point are you connecting the shift-enable net
I assume the output of the mux is going to the logic path (which should be in this case).

1) You can simply tie the input of the flop . it doesn't matter . The state of the flop will be controlled by serial scan chain during scan test.
2) The shift enable signal should be connected to the output of the MUX . In test mode the MUX selects the external pin , where you should apply the shift enable signal to the chip.

 

[ashwinvl]

I think you have given two contradictory statements..
Earlier you said that in test mode it discards the external pin and now you say it selects the external pin..
Eitherways, I feel this doesn't work because the output of the mux is given to the logic path as well as the shift-enable path..In functional mode, this will create problems as the shift-enable signal is liable to change.

 

[Fahmy]

I think you have given two contradictory statements..
Earlier you said that in test mode it discards the external pin and now you say it selects the external pin..
Eitherways, I feel this doesn't work because the output of the mux is given to the logic path as well as the shift-enable path..In functional mode, this will create problems as the shift-enable signal is liable to change.

You are right , my last reply was incorrect . The shift enable signal shall be connected to the output of another AND gate that takes test_enable and external pin as inputs. The Mux is still used to provide the signal to the internal logic.

 

[rca]

so to complete my first description, the path pin_A_for_core used to drive the functional path in the core logic, could be connected during scan mode to an other pin which can be control by the ATPG.

 

[ashwinvl]

Yeah, the inclusion of AND gate is important and is the solution.. I got it..
Thank u guys for your valuable inputs

---------- Post added at 12:22 ---------- Previous post was at 12:10 ----------

so to complete my first description, the path pin_A_for_core used to drive the functional path in the core logic, could be connected during scan mode to an other pin which can be control by the ATPG.

I think in TEST mode the logic path will get its test data from the TEST DATA Pin of the SCAN FLOP, contolled by ATPG, whose DATA pin is connected to the Functional data pin

 

[pavanhs]

HI rca,

can you give me a diagram representing the same logic("Functional data pin can be used as Shift Enable signal")...

Thanks in advance
Pavan HS