Using FPGA control image sample timing

[amekle]

Hi all friends:
I want to use FPGA to control image sample (The image:720×288).Is a good solution using VHDL to program a big counter? have pels signals(13.5Mhz)and row signal.Thnk u!

 

[bibo1978]

can you describe your problem more may be we can find a solution

 

[jamesyang1209]

I don't understand your question:
"Is a good solution using VHDL to program a big counter?"

 

[hoangthanhtung]

I think you can search in **broken link removed**

there is a example about image processing by VHDL and FPGA. A lot of information

 

[bibo1978]

theoretically you can write a VHDL counter for anysize but you have to meet some timing requirements , however 13.5 MHz can be met in modern FPGA with a very large counters "64 bit for example can run at this speed". I am not sure but I have made a pipelined multiplier "48X48 bit that can run more than 80 MHz I assume (really I don't remember the speed but it was but I guess it was 85 MHz)", on Virtex FPGA so I guess the 13.5 MHz can be met with a counter as large as 64 bits which is more than suitable to any application.

 

[amekle]

Thanks! I use video decoder chip SAA7111AHZ.Video formatAL standards .50Hz field frequency.720 active samples(pels) per line.It can give some signalsels signal(13.5Mhz).I want to use FPGA to control sampled data which should be written to SRAM. So FPGA should generate sram address during SAA7111AHZ conversion.I need a good solution.