using for loop in vhdl

hi friends
i need to use a nested loop in vhdl , like this


for j in 0 to 3 loop

for i in j to 3 loop

--------
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end loop
end loop


but this is not acceptable in vhdl , i mean i can't use a variable in the range of a for loop , but i need to do that , so how can i solve that ?

i can't use a variable in the range of a for loop , but i need to do that , so how can i solve that ?

Click to expand...

The solution is simple. loop over the full range, use a conditional statement to restrict the range.

There is nothing wrong with for loops in VHDL. It depends on how you use them that can make them unacceptble.
For simulation, varibles in the ranges are fine. But in a synthesisble system, it has to consider the worst case, so if you use an integer it assumes the variable can be anything from -2^n to 2^n-1, so thats a lot of loops to consider, and way outside the iteration limit.

Why not post the code and show us what you're trying to do?

thanx for your replies , i will complet my code and post it

it's not recommend to use loops in vhdl because it leads to hardware duplication but will make the design run faster, it's better to use state machine, resource sharing, this will improve the area cost

she33

it's not recommend to use loops in vhdl because it leads to hardware duplication but will make the design run faster, it's better to use state machine, resource sharing, this will improve the area cost

Click to expand...

It all depends on what's in the loop. Sometimes the parallel implementation is exactly what you need and the loop contruct a straightforward way to describe a piece of hardware. If it's a complex action, e.g. a bubble sort, I support the FSM idea.

ok, thanx you all , the problem is that iam beginner in vhdl , i wrote some programs which deals with matrices , i will post some of these codes because i need your help to tell me if my code is optimal or there is better ways to write it , i need the smallest area and least execution time in my design


this function calculates the addition of two matrices

package mat_add is

type t11 is array (0 to 9) of unsigned(7 downto 0);
type t1 is array (0 to 9) of t11;

function matadd ( a:t1; b:t1 ) return t1;

end mat_add;

package body mat_add is

function matadd ( a : t1; b:t1 ) return t1 is
variable i,j,k : integer:=0;
variable prod : t1:=(others => (others => (others => '0')));

begin
for i in 0 to 9 loop --(number of rows in the first matrix - 1)
for j in 0 to 9 loop --(number of columns in the second matrix - 1)

prod(i)(j) := (a(i)(j) + b(i)(j));


end loop;
end loop;
return prod;
end matadd;
end mat_add;
-------------------------------------------

i used the same code for subtraction too , and the below codes for matrix multiplication, transpose


package mat_ply is

type t11 is array (0 to 9) of unsigned(7 downto 0);
type t1 is array (0 to 9) of t11; --10*10 matrix
type t22 is array (0 to 9) of unsigned(15 downto 0);
type t2 is array (0 to 9) of t22;


function matmul ( a : t1; b:t1 ) return t2;

end mat_ply;

package body mat_ply is

function matmul ( a : t1; b:t1 ) return t2 is
variable i,j,k : integer:=0;
variable prod : t2:=(others => (others => (others => '0')));

begin
for i in 0 to 9 loop --(number of rows in the first matrix - 1)
for j in 0 to 9 loop --(number of columns in the second matrix - 1)
for k in 0 to 9 loop --(number of rows in the second matrix - 1)

prod(i)(j) := prod(i)(j) + (a(i)(k) * b(k)(j));

end loop;
end loop;
end loop;
return prod;
end matmul;

end mat_ply;

---------------------------------------------------

matrix transpose

package mat_transpose is

type t11 is array (0 to 9) of unsigned(7 downto 0);
type t1 is array (0 to 9) of t11;


function mat_trans( a : t1) return t1;

end mat_transpose;

package body mat_transpose is

function mat_trans ( a : t1) return t1 is
variable i,j : integer range 0 to 11:=0;
variable prod : t1:=(others => (others => (others => '0')));

begin
for i in 0 to 9 loop --(number of rows in the first matrix - 1)
for j in 0 to 9 loop --(number of columns in the second matrix - 1)

prod(i)(j) := a(j)(i);


end loop;
end loop;
return prod;
end mat_trans;

end mat_transpose;

-------------------------------------

now i have this program in matlab , it has a lot of for loops and i want to convert it in vhdl , but i don't know if this is possible , or it is better to use the FSM


for j = 1 : r
for i = j : r
if a(i,j) ~= 0
for k = 1 : r
s = a(j,k); a(j,k) = a(i,k); a(i,k) = s;
s = b(j,k); b(j,k) = b(i,k); b(i,k) = s;
end
t = 1/a(j,j);
for k = 1 : r
a(j,k) = t * a(j,k);
b(j,k) = t * b(j,k);
end
for L = 1 : r
if L ~= j
t = -a(L,j);
for k = 1 : r
a(L,k) = a(L,k) + t * a(j,k);
b(L,k) = b(L,k) + t * b(j,k);
end
end
end
end
break
end
% Display warning if a row full of zeros is found
if a(i,j) == 0
disp('Warning: Singular Matrix')
b = 'error';
return
end
end

The matlab code doesn't tell about suitable FPGA implementation. It runs on a PC and will be always executed sequentially, one matrix element after the other. If you translate it literally to HDL, you'll end up in a fully parallel hardware. For the still handy case of the 10x10 matrix adder, you would e.g. get 100 parallel adders. This can be still feasible in recent FPGA (depending on the number resolution). Parallel matrix multiply might eat up the resources of a large FPGA. (And 10x10 is rather small!) You'll already get the impression that this isn't the way to go.

On the other hand, it's almost pointless to implement the strict sequential processing of a PC on a FPGA, except for a homework excercise. If FPGA arithmetic processing serves a purpose in this case, it's by finding an application specific trade-off between parallel and sequential processing. This means, there's no sense in translating Matlab code to HDL. You need to design a suitable processing scheme, considering application speed requirements, data size, affordable FPGA resources.