biff44
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I am not a DSP guy by any means. But I have a problem that might be best solved by a DSP chip. If I have an IF signal, say at 10 MHz unmodulated carrier, and I want to compute its phase to a resolution of 0.1 degree, how would I have to process it. In other words, what ADC clock rate, how many bits in the ADC, and how many samples of the 10 MHz signal would I have to take to get to that resolution.
I had someone tell me that I can use a digital downconverter (DDC) function to multiply my phase resolution by a factor of 100.
I need to take enough samples to compute the phase, and then very quickly jump to a new signal and do it all over again. I am wondering how long I need to dwell (how many ADC samples) on each signal to get the answer.
I had someone tell me that I can use a digital downconverter (DDC) function to multiply my phase resolution by a factor of 100.
I need to take enough samples to compute the phase, and then very quickly jump to a new signal and do it all over again. I am wondering how long I need to dwell (how many ADC samples) on each signal to get the answer.