Using design compiler for synthesis

[wisemonkey]

Hi,
I will be using design compiler to synthesize design. My design contains `ifdef-`endif blocks. I can compile and simulate it using synopsys vcs as:

vcs +define+<one of possible value for `ifdef> filename.v

That would compile and simulate but I can't seem to find how to synthesize it the same way?

Thanks for inputs

 

[bffgot]

Hi, you can use a .v file include the `define and add this file to sythesis it

 

[wisemonkey]

Thanks bffgot,
but can u please elaborate a little bit? I've never used include before so I may not get idea easily

Thanks

 

[bffgot]

Hi wisemonkey,
u can add `define "one of possible value for `ifdef" in a define.v file, then add this file to sythesis it

 

[dianin]

Thanks bffgot,
but can u please elaborate a little bit? I've never used include before so I may not get idea easily

Thanks

You can create one file consists all parameters and then include that file inside the RTL file. For example you have parameter GATED_CLK and WIDTH_CH , define in one file named test_def.v as follow:

`define GATED_CLK
`define WIDTH_CH

you have to include above file inside your RTL file , for example your RTL file is test.v. Add following line inside the test.v:

`include "test_def.v"
module test (in, out);
----
--
------
endmodule

This will work in DC.

 

[wisemonkey]

Thank you very much dianin and bffgot.
This way it sounds really easy

Thanks again I'll report in if I happen to hit a block again

 

[chipmonkey]

DC supports ifdef in the RTL files.
you can add your defines just like how you do it in vcs

add +define+<VALUE> to the read_verilog command

 

[wisemonkey]

Thanks chipmonkey,
Thats wat I was looking for Now I can test design with add and finally use include file
Btw I assume it would be

 read_verilog {design files} add +define+<value>

Or is it

read_verilog {design files add +define+<value>}

In any case I'll try both. Thanks

 

[chipmonkey]

There is no "add".

command will look like the following:

read_verilog {design files} +define+<value>

replace <value> with what you need to define

 

[wisemonkey]

my bad, Thanks for correcting .
I assumed add is a part of command and yes I know about replacing value

 

[shengkaiyi]

my bad, Thanks for correcting .
I assumed add is a part of command and yes I know about replacing value

In the man page, it is said as below:

NAME
read_file
Reads designs or libraries into memory, or reads libraries into
the shell.

SYNTAX
list read_file
file_list
[-define macro_names]
[-format format_name]
[-ilm]
[-library library_name]
[-rtl]
[-single_file single_file_name]
[-work library_name]
[-scenarios scenario_list]
[-active_scenarios active_scenario_list]
[-names_file file_list]

Data Types
file_list list
macro_names list
format_name string
library_name string
single_file_name string
scenario_list list
active_scenario_list list

SYNTAX for lc_shell
list read_file
file_list

Data Types for lc_shell
file_list list

ARGUMENTS
file_list
Specifies a list of files to read. When specifying more than
one input_file, enclose the list of names in braces ({}).

-define macro_names
Specifies a list of top-level macros for verilog and systemver-
ilog only.

So it should be "-define macro_names"