Using DCM as a delay line in Virtex-5

Hello everybody,

I am going to configure DCM in Virtex-5 to operate as a delay line. can anybody tell me how to perform this configuration??

Thanks,

I told you before you can't use a DCM as a TDC element, it's not designed to behave like a delay line. If you put in a single 0-1 transition to a DCM you won't get anything out of the outputs. A DCM requires a clock on the input and it has requirements on the maximum jitter and the min/max acceptable frequency, since it's behavior is like a PLL. This would be obvious to you, if you had taken the time to read (and understand) the DCM documentation (see pages 48 & 49 for a feature summary).

ads-ee said:

I told you before you can't use a DCM as a TDC element, it's not designed to behave like a delay line. If you put in a single 0-1 transition to a DCM you won't get anything out of the outputs. A DCM requires a clock on the input and it has requirements on the maximum jitter and the min/max acceptable frequency, since it's behavior is like a PLL. This would be obvious to you, if you had taken the time to read (and understand) the DCM documentation (see pages 48 & 49 for a feature summary).

Click to expand...

Thank you for your reply.
I know the functionality of DCM and I've read those pages carefully, but if you refer to Clock Deskew feature especially Fig. 2.4 on page 66, adding a delay to the feedback path is what I am looking for. I want measure and figure out what is the minimum allowed delay that can be added to DCM by spectrum analyzer ? Do you have a rexommendation, please?

Thank you,

msdarvishi said:

I know the functionality of DCM and I've read those pages carefully, but if you refer to Clock Deskew feature especially Fig. 2.4 on page 66, adding a delay to the feedback path is what I am looking for. I want measure and figure out what is the minimum allowed delay that can be added to DCM by spectrum analyzer ?

Click to expand...

It's documented (it's the phase delay and the minimum tap delay is specified as something like a 1/(f*256)), but you can just run any signal through a DCM only clocks. If you haven't gleaned that from the documentation then you don't understand what you've read so far.

So once again, NO you can't use a DCM to delay some arbitrary signal.

msdarvishi said:

Do you have a rexommendation, please?

Click to expand...

You can try instantiating a DCM in a Verilog/VHDL file and connect to the "Delay Line" feed back path and when the tools error out and can't build the design, maybe then you'll believe me. You can waste your time if you like, me I'm not going to waste anymore time with your posts on this subject.

ads-ee said:

It's documented (it's the phase delay and the minimum tap delay is specified as something like a 1/(f*256)), but you can just run any signal through a DCM only clocks. If you haven't gleaned that from the documentation then you don't understand what you've read so far.

So once again, NO you can't use a DCM to delay some arbitrary signal.



You can try instantiating a DCM in a Verilog/VHDL file and connect to the "Delay Line" feed back path and when the tools error out and can't build the design, maybe then you'll believe me. You can waste your time if you like, me I'm not going to waste anymore time with your posts on this subject.

Click to expand...

Dear @ads-ee,

Thank you for your reply. Indeed I am doing this experiment to see it visually. If you refer to all my comment, I am appreciating you and all very politely and cordially. We are scientists and we discuss scientifically. A scientist must have a big heart to be helpful. I will let you know the result of my examination and I thank again for your hints.

Regards,

msdarvishi said:

We are scientists and we discuss scientifically. A scientist must have a big heart to be helpful.

Click to expand...

Speak for yourself, you don't know me or what I do for a living or perhaps you should considering my username is ads-ee as in Electrical Engineer. Ergo I'm not a scientist, I'm an engineer so I build things that work. Hence I don't go around using DCMs for things other than what they are intended to be used for.

Do that as an engineer and you'll be out of a job when the system fails to function properly due to your improperly designed circuit. So go ahead and study the DCM if you like, but don't expect an engineer to know how to force it to be used in a way that it's not suppose to be used.

Now if you'd asked about doing fine phase shifting of the clock outputs using the DRP then that is easy to do and I've done that as part of a design to perform initial power on alignment of the clock and data for past designs.

I see the problem that the OP didn't tell at all what kind of signal he wants to delay.

Everything that isn't a strictly periodical signal with (almost) fixed frequency can't be delayed by a DCM.

FvM said:

I see the problem that the OP didn't tell at all what kind of signal he wants to delay.

Click to expand...

They pretty much implied that the signal was arbitrary from their other thread, when they stated they are trying to use the DCM as part of a TDC. I'm assuming they are trying to implement the TDC using a tapped delay line. So far the OP seems convinced that they can use the DCM for their TDC circuit and they are being highly resistant (stubborn) to being told it's not capable of being used the way they want.

If they really want to delay a signal then they could either use a bunch of FFs in the fabric or for finer resolution, but limited duration they could use the IODELAY elements. Either way they probably won't end up with a great TDC design (just a design that sort of works okay).