fragnen
Full Member level 4
The Verilog has a keyword posedge. Can poedge be used as the the name of one of the input pins of a module in a rtl as below? Can a parameter named posedge be used as shown below in a rtl? Please reply.
module adder (posedge, in1, out1);
input posedge;
input in1;
output out1;
.......
.......
endmodule
module subt( in3, in4, out2....);
parameter posedge;
input in3, in4;
output out2;
.........
.........
endmodule
module adder (posedge, in1, out1);
input posedge;
input in1;
output out1;
.......
.......
endmodule
module subt( in3, in4, out2....);
parameter posedge;
input in3, in4;
output out2;
.........
.........
endmodule