BartlebyScrivener
Member level 5
I am using Quartus to try and synthesize a design and I keep getting the following errors when trying to use a generate block
for code such as
I found a setting to ensure that it knows my code is systemverilog, am I missing something else? The code works fine in modelsim.
Code:
Error (10170): Verilog HDL syntax error at LIB_PPE.sv(25) near text "genvar"; expecting an identifier ("genvar" is a reserved keyword )
Error (10644): Verilog HDL error at LIB_PPE.sv(30): this block requires a namefor code such as
Code:
generate
for (genvar i=0; i<N-1; i++) begin
or gate1 (l_intermediate[i], l_carry[i], i_priority[i]);
and gate2 (o_grant[i], l_intermediate[i], i_request[i]);
and gate3 (l_carry[i+1], l_intermediate[i], ~i_request[i]);
end
endgenerateI found a setting to ensure that it knows my code is systemverilog, am I missing something else? The code works fine in modelsim.