You are using a Xilinx part, they have an ODDR primitives you could use, that would make things simple.
an ODDR has two data inputs and outputs one data output when the clock is high and the other when the clock is low. Therefore you can connect the two bits to each data input and the 40 MHz clock to the clock input and the output will be at an 80 Mbit data rate.
you could use an oserdes, but that is overkill and is typically used to achieve serial rates up to Gbit range. To use the oserdes you could load an 8-bit register with four 2-bit values (10 MHz rate, i.e. 40 MHz/4) and then load that 8-bit value into the oserdes to output a 80 Mbit., but why do all that when the ODDR would be far easier to implement.