User Testbench for Core1553BRT_APB in LiberoSoc

A

Altair99

Newbie
Joined
Sep 12, 2024
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
39
Hello everyone!
In LiberoSoc IDE I'm trying to simulate a remote terminal of the MIL-STD-1553B interface using the IP core Core1553BRT_APB. For this i'm using the User Testbench provided by this core. When I launch RTL simulation (I'm using ModelSim Microsemi Pro 2020.4), it gives me
Code: 
Error (suppressible): (vsim-3584) Module parameter 'ARGVALUE0' not found for override.
Here is the full log:
Code: 
Reading pref.tcl
# do run.do
# Model Technology ModelSim Microsemi Pro vmap 2020.4 Lib Mapping Utility 2020.10 Oct 14 2020
# vmap PolarFire C:/Microsemi/Libero_SoC_v2021.2/Designer/lib/modelsimpro/precompiled/vlog/PolarFire
# Modifying modelsim.ini
# Model Technology ModelSim Microsemi Pro vmap 2020.4 Lib Mapping Utility 2020.10 Oct 14 2020
# vmap CORE1553BRT_APB_LIB ../component/Actel/DirectCore/CORE1553BRT_APB/4.4.100/mti/lib_vlog_eval/CORE1553BRT_APB_LIB
# Modifying modelsim.ini
# Model Technology ModelSim Microsemi Pro vcom 2020.4 Compiler 2020.10 Oct 14 2020
# Start time: 22:17:18 on Sep 12,2024
# vcom -reportprogress 300 -work CORE1553BRT_APB_LIB -force_refresh
# -- Skipping module BFM_1553BBC
# -- Skipping module BFM_APB
# -- Skipping module BFM_MAIN
# -- Skipping module BFMA1l1OII
# -- Skipping module BRT_BACKEND
# -- Skipping module BRT_CWLEGALITY
# -- Skipping module BRT_DECODER
# -- Skipping module BRT_ENCODER
# -- Skipping module BRT_RT1553B
# -- Skipping module CORE1553BRT_APB_C0_CORE1553BRT_APB_C0_0_CORE1553BRT_APB
# -- Skipping module QTRANSCEIVER
# -- Skipping module TB_AMBA
# End time: 22:17:18 on Sep 12,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim Microsemi Pro vlog 2020.4 Compiler 2020.10 Oct 14 2020
# Start time: 22:17:18 on Sep 12,2024
# vlog -reportprogress 300 -work CORE1553BRT_APB_LIB -force_refresh
# -- Refreshing module BFM_1553BBC
# -- Refreshing module BFM_APB
# -- Refreshing module BFM_MAIN
# -- Refreshing module BFMA1l1OII
# -- Refreshing module BRT_BACKEND
# -- Refreshing module BRT_CWLEGALITY
# -- Refreshing module BRT_DECODER
# -- Refreshing module BRT_ENCODER
# -- Refreshing module BRT_RT1553B
# -- Refreshing module CORE1553BRT_APB_C0_CORE1553BRT_APB_C0_0_CORE1553BRT_APB
# -- Refreshing module QTRANSCEIVER
# -- Refreshing module TB_AMBA
# End time: 22:17:18 on Sep 12,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim Microsemi Pro vlog 2020.4 Compiler 2020.10 Oct 14 2020
# Start time: 22:17:18 on Sep 12,2024
# vlog -reportprogress 300 -sv -work CORE1553BRT_APB_LIB D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/amba_eval/core1553brt_apb.v
# -- Compiling module CORE1553BRT_APB_C0_CORE1553BRT_APB_C0_0_CORE1553BRT_APB
#
# Top level modules:
#   CORE1553BRT_APB_C0_CORE1553BRT_APB_C0_0_CORE1553BRT_APB
# End time: 22:17:18 on Sep 12,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim Microsemi Pro vlog 2020.4 Compiler 2020.10 Oct 14 2020
# Start time: 22:17:18 on Sep 12,2024
# vlog -reportprogress 300 "+incdir+D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/Actel/DirectCore/CORE1553BRT_APB/4.4.100/rtl/verilog/tb_amba_eval" "+incdir+D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval" -sv -work CORE1553BRT_APB_LIB D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/Actel/DirectCore/CORE1553BRT_APB/4.4.100/rtl/verilog/tb_amba_eval/qtransceiver.v
# -- Compiling module QTRANSCEIVER
#
# Top level modules:
#   QTRANSCEIVER
# End time: 22:17:18 on Sep 12,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim Microsemi Pro vlog 2020.4 Compiler 2020.10 Oct 14 2020
# Start time: 22:17:18 on Sep 12,2024
# vlog -reportprogress 300 "+incdir+D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0" "+incdir+D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/Actel/DirectCore/CORE1553BRT_APB/4.4.100/rtl/verilog/tb_amba_eval" "+incdir+D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval" -sv -work CORE1553BRT_APB_LIB D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# -- Compiling module TB_AMBA
#
# Top level modules:
#   TB_AMBA
# End time: 22:17:18 on Sep 12,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -L PolarFire -L CORE1553BRT_APB_LIB -t 1ps -pli "C:/Microsemi/Libero_SoC_v2021.2/Designer/lib/modelsimpro/pli/pf_crypto_win_me_pli.dll" CORE1553BRT_APB_LIB.TB_AMBA
# Start time: 22:17:18 on Sep 12,2024
# //  ModelSim Microsemi Pro 2020.4 Oct 14 2020
# //
# //  Copyright 1991-2020 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim Microsemi Pro and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading CORE1553BRT_APB_LIB.TB_AMBA
# Loading CORE1553BRT_APB_LIB.BFM_1553BBC
# Loading CORE1553BRT_APB_LIB.BRT_ENCODER
# Loading CORE1553BRT_APB_LIB.BRT_DECODER
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE0' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE1' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE10' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE11' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE2' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE3' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE4' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE5' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE6' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE7' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE8' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# ** Error (suppressible): (vsim-3584) D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v(342): Module parameter 'ARGVALUE9' not found for override.
#    Time: 0 ps  Iteration: 0  Instance: /TB_AMBA File: D:/Work_Projects/LiberoSoc/UserTestbench_1553BRT/component/work/CORE1553BRT_APB_C0/CORE1553BRT_APB_C0_0/rtl/verilog/tb_amba_eval/tb_amba.v
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./run.do PAUSED at line 14

Below is the code where these parameters are mentioned only once - this is a fragment of the testbench where an instance of the BFM_APB module is called:
Code: 
BFM_APB #( .VECTFILE        ( "core1553brt.vec"),
               .MAX_INSTRUCTIONS( 8192),
               .MAX_STACK       ( 200),
               .TPD             ( 5),
               .DEBUGLEVEL      ( -1),
               .ARGVALUE0       ( VERIF),         
               .ARGVALUE1       ( NRTS),       
               .ARGVALUE2       ( FAMILY),       
               .ARGVALUE3       ( SU_CLKSPD),       
               .ARGVALUE4       ( SU_CLKSYNC),     
               .ARGVALUE5       ( SU_LOCKRT),       
               .ARGVALUE6       ( BCASTEN),     
               .ARGVALUE7       ( SU_LEGMODE),     
               .ARGVALUE8       ( SA30LOOP),     
               .ARGVALUE9       ( INTENBBR),   
               .ARGVALUE10      ( SU_TESTTXTOUTEN),
               .ARGVALUE11      ( SU_INT_POLARITY)
    ) BFM(
        .SYSCLK(SYSCLK),
        .SYSRSTN(SYSRSTN),
        .PCLK(PCLK),
        .PRESETN(PRESETN),
        .PADDR(PADDR),
        .PENABLE(PENABLE),
        .PWRITE(PWRITE),
        .PWDATA(PWDATA),
        .PRDATA(PRDATA),
        .PREADY(PREADY),
        .PSLVERR(PSLVERR),
        .PSEL(PSEL),
        .INTERRUPT(INTERRUPT),
        .GP_OUT(GP_OUT),
        .GP_IN(GP_IN),
        .EXT_WR(EXT_WR),
        .EXT_RD(EXT_RD),
        .EXT_ADDR(EXT_ADDR),
        .EXT_DATA(EXT_DATA),
        .EXT_WAIT(EXT_WAIT),
        .FINISHED(FINISHED),
        .FAILED(FAILED)
    );

As can be seen, ARGVALUE0 - ARGVALUE11 are the parameters of the BFM_APB module, which implements the APB Bus Functional Model. According to the Core1553BRT_APB 4.3 Handbook documentation (p.30), this module generates bus cycles using the core1553brt.bfm command file.Due to the restricted license, the BFM_APB module in my project is provided as a pre-compiled simulation model and is not available for viewing or editing.


I've looked through a lot of documentation (Core1553BRT_APB 4.3 Handbook, Core1553BRT_APB 4.2 Handbook, DirectCore AMBA BFM User's Guide, Libero SoC Design Flow User Guide, SmartDesign User Guide, etc.) and various forums, but I haven't found answers to my questions - what causes this error? And what should I do to fix it?


Maybe I'm very inattentive and inexperienced and missing something obvious, so I'm asking for help.
In any case, I'd appreciate any help. Thanks in advance!
 

Solution
A
Finally, I managed to run this testbench. Initially, I tried to run it on PolarFire family in LiberoSoc v.2021.2:


And I didn't succeed because of the error described in my question.


Then, I tried to run it on other families and I succeeded on IGLOO2 and SmartFusion2. Below is a screenshot of waveforms obtained as a result of running the testbench:
Sort by date Sort by votes
Altair99 said:
Due to the restricted license, the BFM_APB module in my project is provided as a pre-compiled simulation model and is not available for viewing or editing.
Click to expand...
In my opinion you need to take up this matter with the source that provided you the pre-compiled simulation model. Because it is not possible for you to change or for us to view and provide suggestions due to the pre-compiled nature.

Without fully understanding these it is difficult for me to comment.

Code: 
.ARGVALUE1       ( NRTS),       
               .ARGVALUE2       ( FAMILY),       
               .ARGVALUE3       ( SU_CLKSPD),       
               .ARGVALUE4       ( SU_CLKSYNC),     
               .ARGVALUE5       ( SU_LOCKRT),       
               .ARGVALUE6       ( BCASTEN),     
               .ARGVALUE7       ( SU_LEGMODE),     
               .ARGVALUE8       ( SA30LOOP),     
               .ARGVALUE9       ( INTENBBR),   
               .ARGVALUE10      ( SU_TESTTXTOUTEN),
               .ARGVALUE11      ( SU_INT_POLARITY)
 

Upvote 1 Downvote
Thank you for your reply, dpaul!

The source of this pre-compiled simulation model is the Libero Soc IDE. Of course, my first idea was to ask this question on their forum. And the only reason I haven't done it yet is that when I try to register, this site denies me access. I've tried this on different computers, phones, Internet providers and several VPN services. The result is the same - Access Denied. So, I will think about how to work around this issue.

Anyway, thank you for advice!
 

Attachments

  • Снимок экрана от 2024-09-16 22-29-16.png
    43.8 KB · Views: 34

Upvote 0 Downvote
Finally, I managed to run this testbench. Initially, I tried to run it on PolarFire family in LiberoSoc v.2021.2:


And I didn't succeed because of the error described in my question.


Then, I tried to run it on other families and I succeeded on IGLOO2 and SmartFusion2. Below is a screenshot of waveforms obtained as a result of running the testbench:
 

Upvote 0 Downvote
Solution
You must log in or register to reply here.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…