User defined primitives in verilog

I tried simulating the following code in modelsim.

//instantiate primitive
//verilog model:circuit instantiation of circuit_UDP_1

module circuit_with_UDP_1(F,A,B,C,D);
output F;
input A,B,C,D;
UDP_1 (F,A,B,C,D);
endmodule


primitive UDP_1(f,a,b,c,d);
output f;
input a,b,c,d;
//truth table for f=F(a,b,c,d)=summation(7,11,13,14,15)
table
// a b c d : f
0 0 0 0 : 0;
0 0 0 1 : 0;
0 0 1 0 : 0;
0 0 1 1 : 0;
0 1 0 0 : 0;
0 1 0 1 : 0;
0 1 1 0 : 0;
0 1 1 1 : 1;
1 0 0 0 : 0;
1 0 0 1 : 0;
1 0 1 0 : 0;
1 0 1 1 : 1;
1 1 0 0 : 0;
1 1 0 1 : 1;
1 1 1 0 : 1;
1 1 1 1 : 1;
endtable
endprimitive

But I cannot simulate it when I made a right-click on it, my simulate option is disabled and it has 'U' symbol on its left rather than the 'M'.Can anyone tell me, what is the actual bug in this program???If my simulation procedure is wrong, could you please let me know the correct procedure?

Are you a licensed user or demo user?

Licensed user

What software are you using? Mentor Graphics ModelSim or ModelSim Altera Edition?

Am using mentor graphics modelsim