Bartart
Full Member level 2
Hi!
My problem is I have wrote a function with 3 input parameters (integer, integer and std_logic_vector) and return std_logic_vector. This package is synthesible. that OK
but in my VHDL code when I use the function it doesn't work.
the syntax is
SO <= fun 3 6 "101";
the error is
IN mode Formal xfrom of fun with no default value must be associated with an actual value.
any idea how to solve my problem?
bart
My problem is I have wrote a function with 3 input parameters (integer, integer and std_logic_vector) and return std_logic_vector. This package is synthesible. that OK
but in my VHDL code when I use the function it doesn't work.
the syntax is
SO <= fun 3 6 "101";
the error is
IN mode Formal xfrom of fun with no default value must be associated with an actual value.
any idea how to solve my problem?
bart