Use of const in SystemVerilog; what is the proper way of using const for synthesis?

[likewise]

Hello,

I would like to use constants in my SystemVerilog design for synthesis, which allow me to define values with a bit of arithmetic like this:

---

Code Verilog - [expand]
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const mytype_t R = (M + (N << 1)) / (1 + (N << 1)) + 1;
const mytype_t RF = (R + 2**5) / 2**6;
const mytype_t RF = RF > 2? RF: 2;

---

However, I understand that constants are not immediately available at start at runtime.

What exactly does this mean? When *are* they available and how can I use these constants safely?

Here is an example source code, which I try to compile stand-alone using Quartus:

---

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const logic [7:0] c = 8;
 
module systemverilogconst(clk, rstn, a, b);
 
input logic clk;
input logic rstn;
 
input logic [7:0] a;
output logic [7:0] b;
 
logic [7:0] b_next;
 
always_comb
begin
  b_next = a + c;
end
 
always_ff @(posedge clk or negedge rstn) begin
  // asynchronous reset?
  if (~rstn) begin
    b <= '0;
  end
  // clock rising edge
  else begin
    b <= b_next;
  end
end
 
endmodule

---

and below are the critical warnings that Quartus gives.
They tell that c is never read, but my intent is a = b + c;
Also, I would expect c to be 8, but it is 0 (fully tied to GND)

Warning (10036): Verilog HDL or VHDL warning at systemverilogconst.sv(1): object "c" assigned a value but never read
Critical Warning (35046): Net "work.work.c_0_" has a missing source. The net will be connected to GND and its default value will be ignored.
Critical Warning (35046): Net "work.work.c_1_" has a missing source. The net will be connected to GND and its default value will be ignored.
Critical Warning (35046): Net "work.work.c_2_" has a missing source. The net will be connected to GND and its default value will be ignored.
Critical Warning (35046): Net "work.work.c_3_" has a missing source. The net will be connected to GND and its default value will be ignored.
Critical Warning (35046): Net "work.work.c_4_" has a missing source. The net will be connected to GND and its default value will be ignored.
Critical Warning (35046): Net "work.work.c_5_" has a missing source. The net will be connected to GND and its default value will be ignored.
Critical Warning (35046): Net "work.work.c_6_" has a missing source. The net will be connected to GND and its default value will be ignored.
Critical Warning (35046): Net "work.work.c_7_" has a missing source. The net will be connected to GND and its default value will be ignored.

Regards,

Leon.

 

[dave_59]

A const variable in SystemVerilog is a variable that can only be initialized in its declaration, and never assigned another value again. Most synthesis tools ignore these initializations, so they appear as variables that have no drivers. There is also a problem with the order of initialization that can produce unexpected results.

I have a DVCon paper Using Parameterized Classes and Factories that explains the difference between a const and a constant in SystemVerilog. You can ignore the part about classes and just look at the section titled Parameters, Constants, and const

You probably want to use a parameter or localparam if these equations are made up entirely of other parameters or constants. As soon as the equation involves another variable, you may have to use a function or continuous assignment. (SystemVerilog 1800-2009 added a let statement, but most tools have not implemented it yet.

Also, it is not a good practice to put statements outside of a module. Use a package and import the package.

 

[likewise]

Dave,

thank you for your response.

A const variable in SystemVerilog is a variable that can only be initialized in its declaration, and never assigned another value again. Most synthesis tools ignore these initializations, so they appear as variables that have no drivers. There is also a problem with the order of initialization that can produce unexpected results.

But if there is a non-cyclic directional graph of dependencies between those constants, the synthesis tools should be able to neatly synthesize this?
So it is a synthesis tool problem, and for the next few years, we cannot use const usefully.

You probably want to use a parameter or localparam if these equations are made up entirely of other parameters or constants.

The nice thing about const is that it is a typed variable, thus I expected I could even make initialization instances of (packed) structs etc.

One work-around I found to work in my tool is defining a function that returns the const type.

---

Code Verilog - [expand]
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function mytype_t myconst()
begin
  // might even be a packed struct initializer, unlike parameter
  const mytype_t a = mytype_const;
  return mytype_const;
end

---

then in my combinational logic, use "myconst()" instead of "myconst".

Also, it is not a good practice to put statements outside of a module. Use a package and import the package.

Yes, in my real design I have this, for the minimal case source code I posted I compressed it into a small number of lines in a single file that demonstrates my expectations.

Thanks,

Leon.

 

[dave_59]

But if there is a non-cyclic directional graph of dependencies between those constants, the synthesis tools should be able to neatly synthesize this?
So it is a synthesis tool problem, and for the next few years, we cannot use const usefully.[/QUOTE]Unless the standard defines these semantics, there will be simulation/synthesis tool mismatches.

The nice thing about const is that it is a typed variable, thus I expected I could even make initialization instances of (packed) structs etc.
.

Parameters can be typed as well with the same types allowed for variables; structs, arrays, etc.