omar-malek
Member level 5
Hi to all
i have a queqtion about asic syntèesis
now i am in my final year project i want to design a digital filter fir channel selection
so i want to use generic vhdl module but i don't know if crea a probleme after when i passe to the step of synthèsis using synopsys.
i have a queqtion about asic syntèesis
now i am in my final year project i want to design a digital filter fir channel selection
so i want to use generic vhdl module but i don't know if crea a probleme after when i passe to the step of synthèsis using synopsys.