Use Clock Rising and falling edge when running synthesis

[daffo123]

Dear All.

Is there any idea to use both clock rising and falling edge when we run synthesis?

I got an error message when I use both the rising and falling edge in synthesis.

Please let me know if you have ideas or experiences.

Thank you.

 

[haykp]

My belief is that we cannot use the same clock clock rising and falling edges in synthesys, because there is no such flop which works with both rising and falling edges.

 

[chipmonkey]

can you invert the first clock and use the posedge of the resultant clock?

 

[kornukhin]

My belief is that we cannot use the same clock clock rising and falling edges in synthesys, because there is no such flop which works with both rising and falling edges.

Actually there is such flops, called "dual-edge triggered flip-flop". But I'm not sure that vendors have such stabdard cells and EDA tools can operate with it.

 

[alexan_e]

Check my post in the following link
https://www.edaboard.com/threads/133082/#post810676 (VHDL code & testbench , simulation result)

The method i have used is described in this link
https://www.edaboard.com/threads/195444/#post818994.

The other solution is a dual-edge triggered flip-flop but you will not find it in many devices, for example CoolRunner-II CPLDs has it.

Alex

 

[daffo123]

Thank you very much all of responders.

It is very very helpful for me

Best Regards.