Use case for different programming languages for design and testbench?

Hi All,

Sometime back in this forum I had asked some queries pertaining to Behavioural modelling of an elevator-controller. I succeeded in doing the required design in VHDL and the same in Verilog as well. While doing this exercise, I also came to know that it is possible to use a VHDL testbench to simulate a design written in Verilog by using Altera's ModelSim complete version. This VHDL testbench was provided by my instructor and now I'm wondering that, what is the point in doing such kind of simulation. One thing that I could think of is that by using different Testbenches, it is possible that I can verify the design a lot more, but I think I can achieve the same thing by using different testbenches, written in Verilog itself. So why use a VHDL testbench for simulating a Verilog design ? Are their any benefits? Are there any disadvantages too(other than having to learn two different languages to write the testbench) ?

Mixed language designs usually come about because you download some IP in another language. There are no advantages to mixed languages, in some ways it limits the tools you can use as the free and the cheaper end licences only support single language.

Both languages can do pretty much the same stuff.

Mixed language designs usually come about because you download some IP in another language. There are no advantages to mixed languages, in some ways it limits the tools you can use as the free and the cheaper end licences only support single language.

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Thank you. So on one hand, it may save time in verification process(No need to rewrite the testbench in the same language as is the design) and on the other it can cause increased cost from the tools persepective(The need to have such a Simulator). But are there any difference in the simulaion model of these two languages ? I mean, Is there any significant difference between the two (VHDL and Verilog) Simulation ? The reason i ask this, is because If the stimulus in both languages are same then, the resulting waveform is going to be same, except for the need of explicit initialization in case of Verilog ?

Most of the difference is in syntax. They can both be used to design/verify the same RTL code.